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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.


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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815

--- Comment #2 from Ilija Kocho <ilijak@siva.com.mk> ---
Created attachment 2166
  --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2166&action=edit
Bug fix to dspi_transaction_end 130407-0213 increment to Attachment 2164.

This patch fixes a race condition bug in dspi_transaction_end(). The bug was
exposed during Mike Jones testing of bug 1001814. I thank Mike for testing.

The patch is incremental to attachment 2167

Ilija

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