[Bug 1001837] Rich FlexBus RAM layout

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001837

Mike Jones <mjones@linear.com> changed:

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--- Comment #5 from Mike Jones <mjones@linear.com> ---
I am trying to understand the memory layout. It appears that:

0x60C00000 Non-Cached Data RAM 4MB
0x60400000 Cached Data RAM 8MB
0x60000000 Code RAM 4MB

Stacks seem to be in the middle one, because a variable on the stack is at
0x604008D8. This is the variable getting corrupted as discussed in #101764, the
MMC/SPI patch.

>From CDL comments, it appears you can't DMA to cached data. If the SPI driver
uses DMA, I believe it will DMA to arrays on the stack in the cached area.

Do you think this could be the source of my SPI problems that only occur on
FXM? That DMA to the stack area is messing up the stack leading to the bad
address pointers.

Is there a way to disable this cache? 

There is a value CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP, but I am guessing that is
not for the 8MB cached data.

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