RedBoot supports a serial port and the built in ethernet port for communication and downloads. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports flash management for the system flash region.
The following RedBoot configurations are supported:
Unlike other targets, the nanoEngine comes equipped with boot firmware which you cannot modify. See chapter 5, "nanoEngine Firmware" of the nanoEngine Hardware Reference Manual (we refer to "July 17, 2000 Rev 0.6") from Bright Star Engineering.
Because of this, eCos, and therefore Redboot, only supports a special configuration of the ROM mode, starting at offset 0x40000 in the flash.
Briefly, the POST-configuration RedBoot image lives in flash following the BSE firmware. The BSE firmware is configured, using its standard bootcmd command, to run RedBoot at startup.
You can perform the initial load of the POST-configuration RedBoot image into flash using the BSE firmware's load command. This will load a binary file, using TFTP, and program it into flash in one operation. Because no memory management is used in the BSE firmware, flash is mapped from address zero upwards, so the address for the RedBoot POST image is 0x40000. You must use the binary version of RedBoot for this, redboot-post.bin.
This assumes you have set up the other BSE firmware config parameters such that it can communicate over your network to your TFTP server.
>load redboot-post.bin 40000 loading ... erasing blk at 00040000 erasing blk at 00050000 94168 bytes loaded cksum 00008579 done > > set bootcmd "go 40000" > get myip = 10.16.19.198 netmask = 255.255.255.0 eth = 0 gateway = 10.16.19.66 serverip = 10.16.19.66 bootcmd = go 40000 >
NOTE: the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead at 38400 Baud. You must select the right baud rate in your terminal program to be able to set up the BSE firmware.
Boot: BSE 2000 Sep 12 2000 14:00:30 autoboot: "go 40000" [hit ESC to abort]
Once you have installed a bootable RedBoot in the system in this manner, we advise re-installing using the generic method described in Chapter 4 in order that the Flash Image System contains an appropriate description of the flash entries.
The configuration file named redboot_POST.ecm configures RedBoot to build for execution at address 0x50040000 (or, during bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable firmware to live in the lower addresses of the flash and to run before RedBoot gets control. The assumption is that RedBoot will be entered at its base address in physical memory, that is 0x00040000.
Alternatively, for testing, you can call it in an already running system by using go 0x50040040 at another RedBoot prompt, or a branch to that address. The address is where the reset vector points. It is reported by RedBoot's load command and listed by the fis list command, amongst other places.
Using the POST configuration enables a normal config option which causes linking and initialization against memory layout files called "...post..." rather than "...rom..." or "...ram..." in the include/pkgconf directory. Specifically:
Because the nanoEngine contains immutable boot firmware at the start of flash, RedBoot for this target is configured to reserve that area in the Flash Image System, and to create by default an entry for the POST mode RedBoot.
RedBoot> fis list Name FLASH addr Mem addr Length Entry point (reserved) 0x50000000 0x50000000 0x00040000 0x00000000 RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040 RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000 FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000 RedBoot>
The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers installed, but these have no associated serial EEPROM in which to record their Ethernet Station Address (ESA, or MAC address). The BSE firmware records an ESA for the device it uses, but this information is not available to RedBoot; we cannot share it.
To keep the ESAs for the two ethernet interfaces, two new items of RedBoot configuration data are introduced. You can list them with the RedBoot command fconfig -l thus:
RedBoot> fconfig -l Run script at boot: false Use BOOTP for network configuration: false Local IP address: 10.16.19.91 Default server IP address: 10.16.19.66 Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99 Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A GDB connection port: 9000 Network debug at boot time: false RedBoot>
The first level page table is located at physical address 0xc0004000. No second level tables are used.
NOTE: The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B).
Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x003fffff 4Mb FLASH (nCS0) 0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet 0x40000000 - 0x4fffffff External IO or PCI bus 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM 0xc8000000 - 0xcfffffff DRAM Bank 1 - empty 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb 0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet 0x40000000 - 0x4fffffff N N External IO or PCI bus 0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb 0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent 0xe0000000 - 0xe7ffffff Y Y Cache Clean
The ethernet devices use a "PCI window" to communicate with the CPU. This is 1Mb of SDRAM which is shared with the ethernet devices that are on the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI accesses see correct data in the correct order. By default it is configured to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be modified, and indeed must be, if less than 32Mb of SDRAM is installed, via the memory layout tool, or by moving the section __pci_window referred to by symbols CYGMEM_SECTION_pci_window* in the linker script.
Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM bank 0, the code can cope with any of these combinations also; "2 x " in this context means one device in each DRAM Bank.
1 x 8Mb = 8Mb 2 x 8Mb = 16Mb
1 x 16Mb = 16Mb 2 x 16Mb = 32Mb
Startup code detects which is fitted and programs the memory map accordingly. If the device(s) is 8Mb, then there are gaps in the physical memory map, because a high order address bit is not connected. The gaps are the higher 2Mb out of every 4Mb.
The SA11x0 OS timer is used as a polled timer to provide timeout support within RedBoot.
The nano is in the set of SA11X0-based platforms. It uses the arm architectural HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components
The target name is "nano" which includes all these, plus the ethernet driver packages, flash driver, and so on.
The ethernet driver is in two parts:
A generic ether driver for Intel i8255x series devices, specifically the i82559, is devs/eth/intel/i82559. Its package name is CYGPKG_DEVS_ETH_INTEL_I82559.
The platform-specific ether driver is devs/eth/arm/nano. Its package is CYGPKG_DEVS_ETH_ARM_NANO. This tells the generic driver the address in IO memory of the chip, for example, and other configuration details. This driver picks up the ESA from RedBoot's configuration data - unless configured to use a static ESA in the usual manner.
These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:
export TARGET=nano export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/nano
The names of configuration files are listed above with the description of the associated modes.