? packages.patch ? fs/rom/current/support/mk_romfs Index: devs/flash/amd/am29xxxxx/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/flash/amd/am29xxxxx/current/ChangeLog,v retrieving revision 1.17 diff -u -r1.17 ChangeLog --- devs/flash/amd/am29xxxxx/current/ChangeLog 11 Oct 2002 20:09:24 -0000 1.17 +++ devs/flash/amd/am29xxxxx/current/ChangeLog 19 Nov 2002 22:22:54 -0000 @@ -1,3 +1,8 @@ +2002-11-17 Bob Koninckx + + * include/flash_am29xxxxx_parts.inl: + * cdl/flash_am29xxxxx.cdl: Definition for AM29F010 part added. Used by cme555. + 2002-10-11 Gary Thomas * include/flash_am29xxxxx_parts.inl: Index: devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl,v retrieving revision 1.10 diff -u -r1.10 flash_amd_am29xxxxx.cdl --- devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 11 Oct 2002 20:09:24 -0000 1.10 +++ devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 19 Nov 2002 22:22:54 -0000 @@ -67,6 +67,16 @@ display "Number of included variants" } + cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F010 { + display "AMD AM29F010 flash memory support" + default_value 0 + implements CYGINT_DEVS_FLASH_AMD_VARIANTS + description " + When this option is enabled, the AMD flash driver will be + able to recognize and handle the AMD29F010 + part in the family." + } + cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B { display "AMD AM29F040B flash memory support" default_value 0 Index: devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl,v retrieving revision 1.9 diff -u -r1.9 flash_am29xxxxx_parts.inl --- devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 11 Oct 2002 20:09:24 -0000 1.9 +++ devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 19 Nov 2002 22:22:56 -0000 @@ -80,6 +80,17 @@ #define _LAST_BOOTBLOCK (-1) #if CYGNUM_FLASH_WIDTH == 8 +#ifdef CYGHWR_DEVS_FLASH_AMD_AM29F010 + { // AM29F010 + device_id : FLASHWORD(0x20), + block_size : 0x4000 * CYGNUM_FLASH_INTERLEAVE, + block_count: 8, + device_size: 0x20000 * CYGNUM_FLASH_INTERLEAVE, + base_mask : ~(0x20000 * CYGNUM_FLASH_INTERLEAVE - 1), + bootblock : false, + banked : false + }, +#endif #ifdef CYGHWR_DEVS_FLASH_AMD_AM29F040B { // AM29F040B device_id : FLASHWORD(0xa4), Index: devs/serial/powerpc/cme555/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/cme555/current/ChangeLog,v retrieving revision 1.2 diff -u -r1.2 ChangeLog --- devs/serial/powerpc/cme555/current/ChangeLog 23 May 2002 23:01:22 -0000 1.2 +++ devs/serial/powerpc/cme555/current/ChangeLog 19 Nov 2002 22:22:59 -0000 @@ -1,3 +1,7 @@ +2002-11-11 Bob Koninckx + + * src/cme555_serial_with_ints.c: interrupt arbiter slightly modified to make GDB CTRL-C work + 2002-04-24 Bob Koninckx * New package. Index: devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c,v retrieving revision 1.2 diff -u -r1.2 cme555_serial_with_ints.c --- devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 23 May 2002 23:01:22 -0000 1.2 +++ devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 19 Nov 2002 22:23:01 -0000 @@ -207,36 +207,38 @@ // The arbitration isr. // I think this is the best place to implement it. The device driver is the only place // in the code where the knowledge is present about how the hardware is used +// +// Always check receive interrupts. Some rom monitor might be waiting for CTRL-C static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data) { cyg_uint16 status; cyg_uint16 control; -#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A // Do not waist time on unused hardware HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status); HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); +#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A // Do not waist time on unused hardware if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC); - if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) - return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE); #endif -#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B // Do not waist time on unused hardware HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status); HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); +#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B // Do not waist time on unused hardware if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC); - if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) - return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); @@ -415,7 +417,7 @@ arbiter.arbiter = hal_arbitration_isr_qsci; // Install the arbitration isr, Make sure that is is not installed twice - hal_mpc5xx_remove_arbitration_isr(&arbiter); + hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); hal_mpc5xx_install_arbitration_isr(&arbiter); // Create the Tx interrupt, do not enable it yet Index: devs/serial/powerpc/ec555/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/ec555/current/ChangeLog,v retrieving revision 1.2 diff -u -r1.2 ChangeLog --- devs/serial/powerpc/ec555/current/ChangeLog 23 May 2002 23:01:22 -0000 1.2 +++ devs/serial/powerpc/ec555/current/ChangeLog 19 Nov 2002 22:23:01 -0000 @@ -1,3 +1,7 @@ +2002-11-11 Bob Koninckx + + * src/ec555_serial_with_ints: arbiter slightly modified to make GDB-CTRLC work. + 2002-04-24 Bob Koninckx * New package. Index: devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c =================================================================== RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c,v retrieving revision 1.2 diff -u -r1.2 ec555_serial_with_ints.c --- devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 23 May 2002 23:01:22 -0000 1.2 +++ devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 19 Nov 2002 22:23:03 -0000 @@ -207,36 +207,40 @@ // The arbitration isr. // I think this is the best place to implement it. The device driver is the only place // in the code where the knowledge is present about how the hardware is used +// +// Always check receiver interrupts. Some rom monitor might be listening to CTRL-C static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data) { cyg_uint16 status; cyg_uint16 control; -#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A // Do not waist time on unused hardware HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status); HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A // Do not waist time on unused hardware if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC); - if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) - return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE); #endif -#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B // Do not waist time on unused hardware HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status); HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control); + if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) + return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B // Do not waist time on unused hardware if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE)) return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC); - if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE)) - return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); // Don't waist time on unused interrupts // if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE)) // return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE); @@ -415,7 +419,7 @@ arbiter.arbiter = hal_arbitration_isr_qsci; // Install the arbitration isr, Make sure that is is not installed twice - hal_mpc5xx_remove_arbitration_isr(&arbiter); + hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); hal_mpc5xx_install_arbitration_isr(&arbiter); // Create the Tx interrupt, do not enable it yet Index: hal/powerpc/arch/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/ChangeLog,v retrieving revision 1.43 diff -u -r1.43 ChangeLog --- hal/powerpc/arch/current/ChangeLog 5 Aug 2002 12:49:46 -0000 1.43 +++ hal/powerpc/arch/current/ChangeLog 19 Nov 2002 22:23:15 -0000 @@ -1,3 +1,12 @@ +2002-11-14 Bob Koninckx + + * include/hal_arch.h: added definitions for floating point support + with GDB-REMOTE + * include/ppc_stub.h: added definitions for floatings point support + with GDB-REMOTE + * src/ppc_stub.c: added definitions/implementation for floating point + support with GDB-REMOTE + 2002-08-05 Gary Thomas 2002-08-05 Bob Koninckx Index: hal/powerpc/arch/current/include/hal_arch.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/include/hal_arch.h,v retrieving revision 1.11 diff -u -r1.11 hal_arch.h --- hal/powerpc/arch/current/include/hal_arch.h 23 May 2002 23:04:12 -0000 1.11 +++ hal/powerpc/arch/current/include/hal_arch.h 19 Nov 2002 22:23:16 -0000 @@ -200,45 +200,104 @@ //----------------------------------------------------------------------------- // Thread register state manipulation for GDB support. +typedef struct { + cyg_uint32 gpr[32]; // General purpose registers + double f0[16]; // First sixteen floating point regs + cyg_uint32 pc; + cyg_uint32 msr; + cyg_uint32 cr; + cyg_uint32 lr; + cyg_uint32 ctr; + cyg_uint32 xer; + cyg_uint32 mq; +#ifdef CYGHWR_HAL_POWERPC_FPU + double f16[16]; // Last sixteen floating point regs + // Could probably also be inserted in the middle + // Adding them at the end minimises the risk of + // breaking existing implementations that do not + // have floating point registers. +#endif +} GDB_Registers; // Translate a stack pointer as saved by the thread context macros above into // a pointer to a HAL_SavedRegisters structure. #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ (_regs_) = (HAL_SavedRegisters *)(_sp_) +// Copy floating point registers from a HAL_SavedRegisters structure into a +// GDB_Registers structure +#ifdef CYGHWR_HAL_POWERPC_FPU +#define HAL_GET_GDB_FLOATING_POINT_REGISTERS( _gdb_, _regs_ ) \ + CYG_MACRO_START \ + double * _p_ = _gdb_->f0; \ + double * _q_ = _regs_->f; \ + for( _i_ = 0; _i_ < 16; _i_++) \ + *_p_++ = *_q_++; \ + \ + _p_ = _gdb_->f16; \ + for( _i_ = 0; _i_ < 16; _i_++) \ + *_p_++ = *_q_++; \ + CYG_MACRO_END +#else +#define HAL_GET_GDB_FLOATING_POINT_REGISTERS( _gdb_, _regs_ ) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Copy a GDB_Registers structure into a HAL_SavedRegisters structure +#ifdef CYGHWR_HAL_POWERPC_FPU +#define HAL_SET_GDB_FLOATING_POINT_REGISTERS( _regs_, _gdb_) \ + CYG_MACRO_START \ + double * _p_ = _regs_->f; \ + double * _q_ = _gdb_->f0; \ + for( _i_ = 0; _i_ < 16; _i_++) \ + *_p_++ = *_q_++; \ + \ + _q_ = _gdb_->f16; \ + for( _i_ = 0; _i_ < 16; _i_++) \ + *_p_++ = *_q_++; \ + CYG_MACRO_END +#else +#define HAL_SET_GDB_FLOATING_POINT_REGISTERS( _regs_, _gdb_) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + // Copy a set of registers from a HAL_SavedRegisters structure into a // GDB ordered array. #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ CYG_MACRO_START \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ int _i_; \ \ for( _i_ = 0; _i_ < 32; _i_++ ) \ - _regval_[_i_] = (_regs_)->d[_i_]; \ + _gdb_->gpr[_i_] = (_regs_)->d[_i_]; \ \ - _regval_[64] = (_regs_)->pc; \ - _regval_[65] = (_regs_)->msr; \ - _regval_[66] = (_regs_)->cr; \ - _regval_[67] = (_regs_)->lr; \ - _regval_[68] = (_regs_)->ctr; \ - _regval_[69] = (_regs_)->xer; \ + _gdb_->pc = (_regs_)->pc; \ + _gdb_->msr = (_regs_)->msr; \ + _gdb_->cr = (_regs_)->cr; \ + _gdb_->lr = (_regs_)->lr; \ + _gdb_->ctr = (_regs_)->ctr; \ + _gdb_->xer = (_regs_)->xer; \ + HAL_GET_GDB_FLOATING_POINT_REGISTERS(_gdb_, _regs_); \ CYG_MACRO_END // Copy a GDB ordered array into a HAL_SavedRegisters structure. #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ CYG_MACRO_START \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ int _i_; \ \ for( _i_ = 0; _i_ < 32; _i_++ ) \ - (_regs_)->d[_i_] = _regval_[_i_]; \ + (_regs_)->d[_i_] = _gdb_->gpr[_i_]; \ \ - (_regs_)->pc = _regval_[64]; \ - (_regs_)->msr = _regval_[65]; \ - (_regs_)->cr = _regval_[66]; \ - (_regs_)->lr = _regval_[67]; \ - (_regs_)->ctr = _regval_[68]; \ - (_regs_)->xer = _regval_[69]; \ + (_regs_)->pc = _gdb_->pc; \ + (_regs_)->msr = _gdb_->msr; \ + (_regs_)->cr = _gdb_->cr; \ + (_regs_)->lr = _gdb_->lr; \ + (_regs_)->ctr = _gdb_->ctr; \ + (_regs_)->xer = _gdb_->xer; \ + HAL_SET_GDB_FLOATING_POINT_REGISTERS(_regs_, _gdb_); \ CYG_MACRO_END //----------------------------------------------------------------------------- Index: hal/powerpc/arch/current/include/ppc_stub.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/include/ppc_stub.h,v retrieving revision 1.7 diff -u -r1.7 ppc_stub.h --- hal/powerpc/arch/current/include/ppc_stub.h 23 May 2002 23:04:13 -0000 1.7 +++ hal/powerpc/arch/current/include/ppc_stub.h 19 Nov 2002 22:23:17 -0000 @@ -57,11 +57,25 @@ extern "C" { #endif +typedef unsigned long target_register_t; + #define NUMREGS 71 + +#ifdef CYGHWR_HAL_POWERPC_FPU +// The PowerPC has floating point registers that are larger than what it +// can hold in a target_register_t +#define TARGET_HAS_LARGE_REGISTERS +// PowerPC stub has special needs for register handling because flating point +// registers are bigger than the rest. Special put_register and get_register +// are provided +#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1 + +// extra space needed for floating point registers +#define HAL_STUB_REGISTERS_SIZE ((sizeof(GDB_Registers) + sizeof(target_register_t) - 1)/sizeof(target_register_t)) +#endif + #define REGSIZE( _x_ ) (((_x_) >= F0 && (_x_) <= F31) ? 8 : 4) - -typedef unsigned long target_register_t; enum regnames { R0, R1, R2, R3, R4, R5, R6, R7, Index: hal/powerpc/arch/current/src/ppc_stub.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/src/ppc_stub.c,v retrieving revision 1.11 diff -u -r1.11 ppc_stub.c --- hal/powerpc/arch/current/src/ppc_stub.c 23 May 2002 23:04:14 -0000 1.11 +++ hal/powerpc/arch/current/src/ppc_stub.c 19 Nov 2002 22:23:18 -0000 @@ -72,6 +72,10 @@ #include // dbg_currthread_id #endif +#ifndef OFFSETOF +#define OFFSETOF(_struct_, _member_) (int)((char *)(&(((_struct_*)0)->_member_))-(char *)((_struct_*)0)) +#endif + /* Given a trap value TRAP, return the corresponding signal. */ int __computeSignal (unsigned int trap_number) @@ -198,6 +202,88 @@ put_register (PC, pc); } +#ifdef CYGHWR_HAL_POWERPC_FPU +static int +reg_offset(regnames_t reg) +{ + // We let the compiler determine the offsets in order to avoid all + // possible alignment problems + int base_offset; + // 32 general purpose registers + if(reg < F0) return reg * 4; + + // first sixteen floating point regs + base_offset = OFFSETOF(GDB_Registers, f0); + if(reg < F16) return base_offset + ((reg - F0) * 8); + + // last sixteen floating point regs + base_offset = OFFSETOF(GDB_Registers, f16); + if(reg < PC) return base_offset + ((reg - F16) * 8); + + // Other 32 bit regs + if(reg < PS) return(OFFSETOF(GDB_Registers, pc)); + if(reg < CND) return(OFFSETOF(GDB_Registers, msr)); + if(reg < LR) return(OFFSETOF(GDB_Registers, cr)); + if(reg < CNT) return(OFFSETOF(GDB_Registers, lr)); + if(reg < XER) return(OFFSETOF(GDB_Registers, ctr)); + if(reg < MQ) return(OFFSETOF(GDB_Registers, xer)); + + return OFFSETOF(GDB_Registers, mq); +} + +// Return the currently-saved value corresponding to register REG of +// the exception context. +target_register_t +get_register (regnames_t reg) +{ + target_register_t val; + int offset = reg_offset(reg); + + if (REGSIZE(reg) > sizeof(target_register_t)) + return -1; + + val = _registers[offset/sizeof(target_register_t)]; + + return val; +} + +// Store VALUE in the register corresponding to WHICH in the exception +// context. +void +put_register (regnames_t which, target_register_t value) +{ + int offset = reg_offset(which); + + if (REGSIZE(which) > sizeof(target_register_t)) + return; + + _registers[offset/sizeof(target_register_t)] = value; +} + +// Write the contents of register WHICH into VALUE as raw bytes. This +// is only used for registers larger than sizeof(target_register_t). +// Return non-zero if it is a valid register. +int +get_register_as_bytes (regnames_t which, char *value) +{ + int offset = reg_offset(which); + + memcpy (value, (char *)_registers + offset, REGSIZE(which)); + return 1; +} + +// Alter the contents of saved register WHICH to contain VALUE. This +// is only used for registers larger than sizeof(target_register_t). +// Return non-zero if it is a valid register. +int +put_register_as_bytes (regnames_t which, char *value) +{ + int offset = reg_offset(which); + + memcpy ((char *)_registers + offset, value, REGSIZE(which)); + return 1; +} +#endif /*---------------------------------------------------------------------- * Single-step support Index: hal/powerpc/cme555/current/misc/redboot_ROM.ecm =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/cme555/current/misc/redboot_ROM.ecm,v retrieving revision 1.1 diff -u -r1.1 redboot_ROM.ecm --- hal/powerpc/cme555/current/misc/redboot_ROM.ecm 20 May 2002 22:23:33 -0000 1.1 +++ hal/powerpc/cme555/current/misc/redboot_ROM.ecm 19 Nov 2002 22:23:18 -0000 @@ -11,30 +11,30 @@ description "" ; hardware cme555 ; template default ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; package -hardware CYGPKG_HAL_POWERPC current ; package -hardware CYGPKG_HAL_POWERPC_MPC5xx current ; package -hardware CYGPKG_HAL_POWERPC_CME555 current ; package -hardware CYGPKG_DEVS_FLASH_CME555 current ; package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; - package -template CYGPKG_HAL current ; - package -template CYGPKG_INFRA current ; package CYGPKG_REDBOOT current ; - package CYGPKG_LIBC current ; - package CYGPKG_LIBC_STRING current ; package CYGPKG_ISOINFRA current ; - package CYGPKG_IO_FLASH current ; package CYGPKG_COMPRESS_ZLIB current ; + package CYGPKG_CRC current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; }; cdl_option CYGBLD_GLOBAL_CFLAGS { user_value "-mcpu=505 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -mmultiple -fno-rtti -fno-exceptions -finit-priority" }; -cdl_option CYGBLD_GLOBAL_LDFLAGS { - user_value "-mcpu=505 -g -nostdlib -Wl,--gc-sections -Wl,-static" +cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { + user_value 1 }; -cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS { +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { user_value 0 }; @@ -46,14 +46,18 @@ user_value 0 }; -cdl_option CYGSEM_HAL_DIAG_MANGLER { - user_value GDB +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 1 }; cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { user_value 4096 }; +cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING { + user_value 0 +}; + cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { user_value 0 }; @@ -78,30 +82,58 @@ user_value 1 }; -cdl_option CYGSEM_HAL_ROM_MONITOR { +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + user_value 0 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE { + user_value 0 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE { user_value 1 }; -cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { user_value 0 }; -cdl_option CYGDBG_HAL_POWERPC_FRAME_WALLS { +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { user_value 0 }; cdl_component CYGPKG_HAL_POWERPC_MPC555 { - inferred_value 1 + user_value 1 }; cdl_option CYGHWR_HAL_POWERPC_FPU { user_value 1 }; -cdl_option CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT { - user_value 0 -}; - cdl_option CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE { user_value 0 }; @@ -118,16 +150,16 @@ user_value 0 }; -cdl_option CYGBLD_BUILD_VERSION_TOOL { - user_value 0 -}; - cdl_component CYG_HAL_STARTUP { user_value ROM }; -cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { - user_value 1 +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + user_value 38400 +}; + +cdl_component CYGPKG_INFRA_DEBUG { + user_value 0 }; cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY { @@ -142,11 +174,11 @@ user_value 0 }; -cdl_component CYGBLD_BUILD_REDBOOT { +cdl_option CYGSEM_REDBOOT_ELF { user_value 1 }; -cdl_option CYGBLD_BUILD_REDBOOT_WITH_ZLIB { +cdl_component CYGBLD_BUILD_REDBOOT { user_value 1 }; @@ -155,75 +187,47 @@ }; cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { - user_value 1 "CME555/MPC555 ROM-Startup" + user_value 1 CME555BK100 }; cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING { - user_value 0 -}; - -cdl_option CYGPKG_REDBOOT_ANY_CONSOLE { - user_value 1 + user_value 3 }; -cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS { +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM { user_value 1 }; -cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { - user_value 0x00020000 -}; - -cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { - user_value 0x00000000 -}; - -cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { - user_value 0x00000000 +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 }; -cdl_option CYGIMP_LIBC_STRING_INLINES { +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { user_value 1 }; -cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { user_value 1 }; -cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { - inferred_value 0 -}; - -cdl_option CYGBLD_ISO_CTYPE_HEADER { - user_value 0 0 -}; - -cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { - user_value 1 -}; - -cdl_option CYGBLD_ISO_ERRNO_HEADER { - user_value 1 -}; - -cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { - user_value 1 +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 }; -cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER { +cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT { user_value 0 0 }; -cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { - user_value 1 +cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER { + user_value 0 }; -cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { - user_value 1 +cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE { + user_value 32000 }; cdl_option CYGBLD_ISO_STRERROR_HEADER { - user_value 1 + user_value 0 0 }; cdl_option CYGBLD_ISO_STRTOK_R_HEADER { @@ -235,7 +239,7 @@ }; cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { - inferred_value 1 + user_value 1 }; cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { @@ -246,10 +250,18 @@ user_value 1 }; +cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC { + user_value 0 +}; + cdl_option CYGNUM_FLASH_WORKSPACE_SIZE { user_value 0x00000000 }; +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F010 { + user_value 0 +}; + cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV200 { user_value 1 }; @@ -258,7 +270,7 @@ user_value 1 }; -cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC { +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 { user_value 0 }; Index: hal/powerpc/ec555/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/ec555/current/ChangeLog,v retrieving revision 1.2 diff -u -r1.2 ChangeLog --- hal/powerpc/ec555/current/ChangeLog 23 May 2002 23:04:19 -0000 1.2 +++ hal/powerpc/ec555/current/ChangeLog 19 Nov 2002 22:23:19 -0000 @@ -1,3 +1,8 @@ +2002-11-11 Bob Koninckx + + * src/ec555.S: Removed statements to disable processor serialization, + this is already done in the variant initialization code. + 2002-05-13 Jesper Skov * cdl/hal_powerpc_ec555.cdl: Removed implemntation of Index: hal/powerpc/ec555/current/misc/redboot_ROM.ecm =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/ec555/current/misc/redboot_ROM.ecm,v retrieving revision 1.1 diff -u -r1.1 redboot_ROM.ecm --- hal/powerpc/ec555/current/misc/redboot_ROM.ecm 20 May 2002 22:23:37 -0000 1.1 +++ hal/powerpc/ec555/current/misc/redboot_ROM.ecm 19 Nov 2002 22:23:20 -0000 @@ -11,30 +11,30 @@ description "" ; hardware ec555 ; template default ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; package -hardware CYGPKG_HAL_POWERPC current ; package -hardware CYGPKG_HAL_POWERPC_MPC5xx current ; package -hardware CYGPKG_HAL_POWERPC_EC555 current ; package -hardware CYGPKG_DEVS_FLASH_EC555 current ; package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; - package -template CYGPKG_HAL current ; - package -template CYGPKG_INFRA current ; package CYGPKG_REDBOOT current ; - package CYGPKG_LIBC current ; - package CYGPKG_LIBC_STRING current ; package CYGPKG_ISOINFRA current ; - package CYGPKG_IO_FLASH current ; package CYGPKG_COMPRESS_ZLIB current ; + package CYGPKG_CRC current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; }; cdl_option CYGBLD_GLOBAL_CFLAGS { user_value "-mcpu=505 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -mmultiple -fno-rtti -fno-exceptions -finit-priority" }; -cdl_option CYGBLD_GLOBAL_LDFLAGS { - user_value "-mcpu=505 -g -nostdlib -Wl,--gc-sections -Wl,-static" +cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { + user_value 1 }; -cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS { +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { user_value 0 }; @@ -46,14 +46,18 @@ user_value 0 }; -cdl_option CYGSEM_HAL_DIAG_MANGLER { - user_value GDB +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 1 }; cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { user_value 4096 }; +cdl_option CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING { + user_value 0 +}; + cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { user_value 0 }; @@ -78,30 +82,58 @@ user_value 1 }; -cdl_option CYGSEM_HAL_ROM_MONITOR { +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + user_value 0 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INHERIT_CONSOLE { + user_value 0 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE { user_value 1 }; -cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { user_value 0 }; -cdl_option CYGDBG_HAL_POWERPC_FRAME_WALLS { +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { user_value 0 }; cdl_component CYGPKG_HAL_POWERPC_MPC555 { - inferred_value 1 + user_value 1 }; cdl_option CYGHWR_HAL_POWERPC_FPU { user_value 1 }; -cdl_option CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT { - user_value 0 -}; - cdl_option CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE { user_value 0 }; @@ -118,16 +150,16 @@ user_value 0 }; -cdl_option CYGBLD_BUILD_VERSION_TOOL { - user_value 0 -}; - cdl_component CYG_HAL_STARTUP { user_value ROM }; -cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { - user_value 1 +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + user_value 38400 +}; + +cdl_component CYGPKG_INFRA_DEBUG { + user_value 0 }; cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY { @@ -142,11 +174,11 @@ user_value 0 }; -cdl_component CYGBLD_BUILD_REDBOOT { +cdl_option CYGSEM_REDBOOT_ELF { user_value 1 }; -cdl_option CYGBLD_BUILD_REDBOOT_WITH_ZLIB { +cdl_component CYGBLD_BUILD_REDBOOT { user_value 1 }; @@ -155,75 +187,47 @@ }; cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { - user_value 1 "EC555/MPC555 ROM-Startup" + user_value 1 EC555BK100 }; cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING { - user_value 0 + user_value 3 }; -cdl_option CYGPKG_REDBOOT_ANY_CONSOLE { +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CKSUM { user_value 1 }; -cdl_option CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS { - user_value 1 -}; - -cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { - user_value 0x00020000 -}; - -cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { - user_value 0x00000000 -}; - -cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { - user_value 0x00000000 +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 }; -cdl_option CYGIMP_LIBC_STRING_INLINES { +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { user_value 1 }; -cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { user_value 1 }; -cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { - inferred_value 0 -}; - -cdl_option CYGBLD_ISO_CTYPE_HEADER { - user_value 0 0 -}; - -cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { - user_value 1 -}; - -cdl_option CYGBLD_ISO_ERRNO_HEADER { - user_value 1 -}; - -cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { - user_value 1 +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 }; -cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER { +cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT { user_value 0 0 }; -cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { - user_value 1 +cdl_component CYGOPT_REDBOOT_FIS_ZLIB_COMMON_BUFFER { + user_value 0 }; -cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { - user_value 1 +cdl_option CYGNUM_REDBOOT_FIS_ZLIB_COMMON_BUFFER_SIZE { + user_value 32000 }; cdl_option CYGBLD_ISO_STRERROR_HEADER { - user_value 1 + user_value 0 0 }; cdl_option CYGBLD_ISO_STRTOK_R_HEADER { @@ -235,7 +239,7 @@ }; cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { - inferred_value 1 + user_value 1 }; cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { @@ -246,24 +250,16 @@ user_value 1 }; -cdl_option CYGNUM_FLASH_WORKSPACE_SIZE { - user_value 0x00000000 -}; - -cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV200 { +cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC { user_value 0 }; -cdl_option CYGHWR_DEVS_FLASH_ST_M29W200B { - user_value 0 +cdl_option CYGNUM_FLASH_WORKSPACE_SIZE { + user_value 0x00000000 }; cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 { user_value 1 -}; - -cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC { - user_value 0 }; Index: hal/powerpc/ec555/current/src/ec555.S =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/ec555/current/src/ec555.S,v retrieving revision 1.2 diff -u -r1.2 ec555.S --- hal/powerpc/ec555/current/src/ec555.S 23 May 2002 23:04:20 -0000 1.2 +++ hal/powerpc/ec555/current/src/ec555.S 19 Nov 2002 22:23:20 -0000 @@ -185,12 +185,6 @@ lwi r4, 0x60000000 lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE) stwx r4, r3, r5 - - // Finally, disable serialization - // Motorola claims that failing to do so results in a performance - // penalty of a facor three !! - lwi r0, 0x00000007 - mtspr 158, r0 #endif sync blr Index: hal/powerpc/ec555/current/src/hal_diag.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/ec555/current/src/hal_diag.c,v retrieving revision 1.2 diff -u -r1.2 hal_diag.c --- hal/powerpc/ec555/current/src/hal_diag.c 23 May 2002 23:04:20 -0000 1.2 +++ hal/powerpc/ec555/current/src/hal_diag.c 19 Nov 2002 22:23:21 -0000 @@ -146,12 +146,12 @@ //----------------------------------------------------------------------------- typedef struct { - cyg_uint16* base; - cyg_int32 msec_timeout; - int siu_vector; - int imb3_vector; - unsigned int level; - int baud_rate; + cyg_uint16* base; // Base address of the register set + cyg_int32 msec_timeout; // How long do we wait + int imb3_vector; // The vector on the IMB3. No need to worry + // about SIU levels or vectors, that's the + // responsibility of the application + int baud_rate; } channel_data_t; //----------------------------------------------------------------------------- @@ -163,49 +163,50 @@ switch(__ch_data->baud_rate) { - case 300: + case 300: br = CYG_DEV_SERIAL_RS232_SCxBR_300; - break; - case 600: + break; + case 600: br = CYG_DEV_SERIAL_RS232_SCxBR_600; - break; - case 1200: + break; + case 1200: br = CYG_DEV_SERIAL_RS232_SCxBR_1200; - break; - case 2400: + break; + case 2400: br = CYG_DEV_SERIAL_RS232_SCxBR_2400; - break; - case 4800: + break; + case 4800: br = CYG_DEV_SERIAL_RS232_SCxBR_4800; - break; - case 9600: + break; + case 9600: br = CYG_DEV_SERIAL_RS232_SCxBR_9600; - break; - case 14400: + break; + case 14400: br = CYG_DEV_SERIAL_RS232_SCxBR_14400; - break; - case 19200: + break; + case 19200: br = CYG_DEV_SERIAL_RS232_SCxBR_19200; - break; - case 28800: + break; + case 28800: br = CYG_DEV_SERIAL_RS232_SCxBR_28800; - break; - case 38400: + break; + case 38400: br = CYG_DEV_SERIAL_RS232_SCxBR_38400; - break; - case 57600: + break; + case 57600: br = CYG_DEV_SERIAL_RS232_SCxBR_57600; - break; - case 115200: + break; + case 115200: br = CYG_DEV_SERIAL_RS232_SCxBR_115200; - break; - default: - // Use the default if something unknown is requested + break; + default: + // Use the default if something unknown is requested br = CYG_DEV_SERIAL_RS232_SCxBR_38400; - break; + break; } - // 8-1-No parity + // 8-1-No parity, enable transmitter and receiver, leave interrupts + // as they are HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE)); // Set baud rate @@ -271,16 +272,12 @@ // flash .... static channel_data_t channels[2] = { { (cyg_uint16*)CYG_DEV_SERIAL_BASE_A, - 1000, - CYGNUM_HAL_INTERRUPT_SIU_LVL0, + 1000, CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, - 0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, { (cyg_uint16*)CYG_DEV_SERIAL_BASE_B, 1000, - CYGNUM_HAL_INTERRUPT_SIU_LVL0, CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, - 0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } }; @@ -342,31 +339,31 @@ ret = chan->baud_rate; break; case __COMMCTL_SETBAUD: - { - va_list ap; - va_start(ap, __func); + { + va_list ap; + va_start(ap, __func); - ret = chan->baud_rate; - chan->baud_rate = va_arg(ap, cyg_int32); - init_serial_channel(chan); + ret = chan->baud_rate; + chan->baud_rate = va_arg(ap, cyg_int32); + init_serial_channel(chan); - va_end(ap); - } - break; + va_end(ap); + } + break; case __COMMCTL_IRQ_ENABLE: - HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level); - HAL_INTERRUPT_UNMASK(chan->imb3_vector); - HAL_INTERRUPT_UNMASK(chan->siu_vector); + // Just enable the interrupt on the IMB3. The debugged application is + // must make sure that the interrupt is properly decoded + HAL_INTERRUPT_UNMASK(chan->imb3_vector); irq_state = 1; break; case __COMMCTL_IRQ_DISABLE: + // Same remark as above ret = irq_state; irq_state = 0; HAL_INTERRUPT_MASK(chan->imb3_vector); - HAL_INTERRUPT_MASK(chan->siu_vector); break; case __COMMCTL_DBG_ISR_VECTOR: - ret = chan->siu_vector; + ret = chan->imb3_vector; break; case __COMMCTL_SET_TIMEOUT: { @@ -378,7 +375,7 @@ va_end(ap); } - break; + break; default: break; } @@ -412,8 +409,8 @@ if(cyg_hal_is_break(&c, 1)) *__ctrlc = 1; - HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector); - res = CYG_ISR_HANDLED; + HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector); + res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); Index: hal/powerpc/mpc5xx/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/ChangeLog,v retrieving revision 1.2 diff -u -r1.2 ChangeLog --- hal/powerpc/mpc5xx/current/ChangeLog 23 May 2002 23:04:26 -0000 1.2 +++ hal/powerpc/mpc5xx/current/ChangeLog 19 Nov 2002 22:23:22 -0000 @@ -1,3 +1,16 @@ +2002-11-11 Bob Koninckx + + * include/var_regs.h: Removed double definitions for ICTRL, ICTRL_SERSHOW + and ICTRL_NOSERSHOW + * src/var_intr.c: Added a very simple serial arbitration isr to make GDB-CTRC + work in the absence of any device drivers. + * include/var_intr.h: Added a definition for hal_arbitration_isr_sci + * include/variant.inc: Make sure FREEZE gets negated before returning from an + exception. Failing to do so prevents proper operation of timers etc when + debugging. + * tests/intr0.c: completely rewritten to something that actually tests something. + Not completely finished. + 2002-04-25 Bob Koninckx 2002-04-25 Jonathan Larmour Index: hal/powerpc/mpc5xx/current/include/var_intr.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/include/var_intr.h,v retrieving revision 1.2 diff -u -r1.2 var_intr.h --- hal/powerpc/mpc5xx/current/include/var_intr.h 23 May 2002 23:04:26 -0000 1.2 +++ hal/powerpc/mpc5xx/current/include/var_intr.h 19 Nov 2002 22:23:29 -0000 @@ -79,8 +79,8 @@ externC void hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data *adata); -externC void -hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data *adata); +externC hal_mpc5xx_arbitration_data * +hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority); //----------------------------------------------------------------------------- // Exception vectors. @@ -2709,6 +2709,8 @@ CYG_ADDRWORD data); externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector, CYG_ADDRWORD data); +externC cyg_uint32 hal_arbitration_isr_sci (CYG_ADDRWORD vector, + CYG_ADDRWORD data); //----------------------------------------------------------------------------- // Symbols used by assembly code Index: hal/powerpc/mpc5xx/current/include/var_regs.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/include/var_regs.h,v retrieving revision 1.2 diff -u -r1.2 var_regs.h --- hal/powerpc/mpc5xx/current/include/var_regs.h 23 May 2002 23:04:26 -0000 1.2 +++ hal/powerpc/mpc5xx/current/include/var_regs.h 19 Nov 2002 22:23:32 -0000 @@ -82,7 +82,6 @@ #define CYGARC_REG_CMPH 155 #define CYGARC_REG_LCTRL1 156 #define CYGARC_REG_LCTRL2 157 -#define CYGARC_REG_ICTRL 158 #define CYGARC_REG_BAR 159 #define CYGARC_REG_MI_GRA 528 #define CYGARC_REG_L2U_GRA 536 @@ -129,7 +128,6 @@ # define CMPH CYGARC_REG_CMPH # define LCTRL1 CYGARC_REG_LCTRL1 # define LCTRL2 CYGARC_REG_LCTRL2 -# define ICTRL CYGARC_REG_ICTRL # define BAR CYGARC_REG_BAR # define MI_GRA CYGARC_REG_MI_GRA # define L2U_GRA CYGARC_REG_L2U_GRA Index: hal/powerpc/mpc5xx/current/include/variant.inc =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/include/variant.inc,v retrieving revision 1.2 diff -u -r1.2 variant.inc --- hal/powerpc/mpc5xx/current/include/variant.inc 23 May 2002 23:04:26 -0000 1.2 +++ hal/powerpc/mpc5xx/current/include/variant.inc 19 Nov 2002 22:23:33 -0000 @@ -154,6 +154,12 @@ ##----------------------------------------------------------------------------- ## MPC5xx exception state handling .macro hal_variant_save regs +#ifdef CYGSEM_HAL_ROM_MONITOR + ## This is not really a save of this registers. It just clears any pending + ## flags so that vwe can be sure that FREEZE will be negated after returning + ## from the interrupt. Failing to do can block a number of devices. + mfspr r3, 148; +#endif .endm .macro hal_variant_load regs Index: hal/powerpc/mpc5xx/current/src/var_intr.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/src/var_intr.c,v retrieving revision 1.2 diff -u -r1.2 var_intr.c --- hal/powerpc/mpc5xx/current/src/var_intr.c 23 May 2002 23:04:26 -0000 1.2 +++ hal/powerpc/mpc5xx/current/src/var_intr.c 19 Nov 2002 22:23:34 -0000 @@ -153,6 +153,42 @@ return 0; } +// Default arbitration ISR for serial interrupts. Although such arbitration +// belongs in the serial device driver, we require this default implementation +// for CTRL-C interrupts to be delivered correctly to any running ROM monitor. +// A device driver that uses more than just receive interrupts may of course +// provide its own arbiter. +externC cyg_uint32 +hal_arbitration_isr_sci(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + cyg_uint32 isr_ret; + cyg_uint16 scc_sr; + cyg_uint16 scc_cr; + + // Try SCI0 + HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scc_sr); + HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, scc_cr); + if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) { + isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX); +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + if (isr_ret & CYG_ISR_HANDLED) +#endif + return isr_ret; + } + + HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scc_sr); + HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, scc_cr); + if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) { + isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX); +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + if (isr_ret & CYG_ISR_HANDLED) +#endif + return isr_ret; + } + + return 0; +} + // ------------------------------------------------------------------------- // IMB3 interrupt decoding // @@ -212,36 +248,48 @@ return (hal_mpc5xx_arbitration_data *)(tmp.reserved); } +// This returns either the removed object or NULL if the priority +// was not found in the list. +// If a valid pointer is returned, the new start of the list is chained to it. static hal_mpc5xx_arbitration_data * mpc5xx_remove(hal_mpc5xx_arbitration_data * list, - hal_mpc5xx_arbitration_data * data) + cyg_uint32 apriority) { - hal_mpc5xx_arbitration_data tmp; + hal_mpc5xx_arbitration_data tmp; + hal_mpc5xx_arbitration_data result = 0; hal_mpc5xx_arbitration_data * ptmp = &tmp; tmp.reserved = list; while(ptmp->reserved) { - if(ptmp->reserved == data) + if(((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->priority == apriority) break; + // move on ptmp = (hal_mpc5xx_arbitration_data *)(ptmp->reserved); } + // When we come here, ptmp is either chained to NULL or to the one we were looking for. if(ptmp->reserved) + { // remove it + result = (hal_mpc5xx_arbitration_data *)(ptmp->reserved); + result->reserved = tmp.reserved; + ptmp->reserved = ((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->reserved; + } - return (hal_mpc5xx_arbitration_data *)(tmp.reserved); + return result; } #endif externC void hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data * adata) -{ +{ // Find the SIU vector from the priority CYG_ADDRWORD vector = 2*(1 + adata->priority); + if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7) - { - HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, 0); + { // Store adata in the objects table + HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, adata); HAL_INTERRUPT_UNMASK(vector); } else @@ -253,31 +301,74 @@ imb3_data_head = mpc5xx_insert(imb3_data_head, adata); HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); #else - HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, 0); + HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, adata); HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); #endif } } -externC void -hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data * adata) +externC hal_mpc5xx_arbitration_data * +hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority) { + hal_mpc5xx_arbitration_data * result = 0; + + // Find the SIU vector from the priority + CYG_ADDRWORD vector = 2*(1 + apriority); + if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7) + { + result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[vector]); + HAL_INTERRUPT_DETACH(vector, hal_interrupt_handlers[vector]); + } + else + { #ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER - // Prevent anything from coming through while manipulating the list - HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); - imb3_data_head = mpc5xx_remove(imb3_data_head, adata); - HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); + // Prevent anything from coming through while manipulating the list + HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); + result = mc5xx_remove(imb3_data_head, apriority); + + // If something was removed, update the list. + if(result) imb3_data_head = result->reserved; + HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); +#else + result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[CYGNUM_HAL_INTERRUPT_SIU_LVL7]); + HAL_INTERRUPT_DETACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SIU_LVL7]); #endif + } + + return result; } // ------------------------------------------------------------------------- // Variant specific interrupt setup +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) +static hal_mpc5xx_arbitration_data sci_arbiter; +#endif + externC void hal_variant_IRQ_init(void) { #ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0); HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7); +#endif + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) + // GDB-CTRLC + // Install a default arbiter for serial interrupts. This allows + // to make a boot monitor simply turn on the required Rx interrupt + // and still be delivered the necessary default isr. Without this, + // redboot would be informed of a level interrupt on the SIU instead + // of the Rx interrupt that really happened. + // Make sure the interrupts are set up on the correct level + sci_arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI; + sci_arbiter.data = 0; + sci_arbiter.arbiter = hal_arbitration_isr_sci; + + hal_mpc5xx_install_arbitration_isr(&sci_arbiter); + HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); + HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI); #endif } Index: hal/powerpc/mpc5xx/current/tests/intr0.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc5xx/current/tests/intr0.c,v retrieving revision 1.2 diff -u -r1.2 intr0.c --- hal/powerpc/mpc5xx/current/tests/intr0.c 23 May 2002 23:04:27 -0000 1.2 +++ hal/powerpc/mpc5xx/current/tests/intr0.c 19 Nov 2002 22:23:35 -0000 @@ -40,268 +40,191 @@ //================================================================= //#####DESCRIPTIONBEGIN#### // -// Author(s): jskov -// Contributors: jskov -// Date: 1998-12-01 -// Description: Simple test of MPC860 interrupt handling when the +// Author(s): Bob Koninckx +// Contributors: Bob Koninckx +// Date: 2002-11-16 +// Description: Simple test of MPC5xx interrupt handling when the // kernel has not been configured. Uses timer interrupts. // Options: //####DESCRIPTIONEND#### -//#define DEBUG_PRINTFS -#ifdef DEBUG_PRINTFS -extern diag_printf( char *format, ... ); -#endif - #include - -#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS -#include - -#include +#include #include +#include -#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE - -#undef CHECK(b) -#define CHECK(b) CYG_TEST_CHECK(b,#b) +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include +#include +#include -// Can't rely on Cyg_Interrupt class being defined. -#define Cyg_InterruptHANDLED 1 +#define ID_RTC_SEC 12345 +#define ID_RTC_ALR 23451 +#define ID_PIT 34512 +#define ID_TBA 45123 +#define ID_TBB 51234 -// This is the period between interrupts, measured in decrementer ticks. -// Period must be longer than the time required for setting up all the -// interrupt handlers. +#define CYG_InterruptHANDLED 1 #define PIT_PERIOD 5000 +#define TB_PERIOD (PIT_PERIOD*160) -#ifdef CYGPKG_HAL_POWERPC_MBX -#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS -#else -#define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors -#endif - -#define ID_RTC_SEC 12345 -#define ID_RTC_ALR 23451 -#define ID_PIT 34512 -#define ID_TBA 45123 -#define ID_TBB 51234 +// Factor 160 comes from setting SCCR = 0x0300. Thus, TBS = 1 -->> Time base is clocked by +// system clock / 16 = 40MHz / 16 +// RTDIV = 1 -->> RTC/PIT clocked by OSCM / 256 +// or 4 MHz / 256 +// Factor of 160 between the two volatile cyg_uint32 count = 0; - -// Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10 -// Interrupt PIT TBA PIT PIT TBB PIT PIT -// pit_count 0 0 0 1 1 2 2 3 3 4 4 -// count 0 0 1 3 4 4 5 40 41 42 - -static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42}; static int pit_count = 0; +static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42}; // These are useful for debugging: static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1}; static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1}; -// Periodic timer ISR. Should be executing 5 times. -static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - cyg_uint32 verify_value; - - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!"); - CYG_ASSERT (ID_PIT == data, "Wrong data!"); - - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT); - - count++; - - count_actual_table[pit_count] = count; - { - cyg_uint32 tbl; - CYGARC_MFTB (TBL_R, tbl); - tbr_actual_table[pit_count] = tbl; - } - - verify_value = count_verify_table[pit_count++]; - -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_PIT executed %d of 5\n", pit_count ); -#endif - - CYG_ASSERT (count == verify_value, "Count wrong!"); - - // End of test when count is 42. Mask interrupts and print PASS text. - if (42 <= count || 5 == pit_count) { - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - -#ifdef DEBUG_PRINTFS - diag_printf( "INFO: Actual counts: %d %d %d %d %d\n", - count_actual_table[0], - count_actual_table[1], - count_actual_table[2], - count_actual_table[3], - count_actual_table[4] ); - diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n", - tbr_actual_table[0], - tbr_actual_table[1], - tbr_actual_table[2], - tbr_actual_table[3], - tbr_actual_table[4] ); -#endif - if (42 == count && 5 == pit_count) - CYG_TEST_PASS_FINISH("Intr 0 OK"); - else - CYG_TEST_FAIL_FINISH("Intr 0 Failed."); - } - - return Cyg_InterruptHANDLED; -} +hal_mpc5xx_arbitration_data hal_arbitration_data_tb; +hal_mpc5xx_arbitration_data hal_arbitration_data_pit; -// TimeBase A ISR. Should be executing once. static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data) { - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!"); + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!"); CYG_ASSERT (ID_TBA == data, "Wrong data!"); - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - - count = count * 3; + HAL_INTERRUPT_ACKNOWLEDGE(vector); + count = count*3; -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_TBA executed\n" ); -#endif - - return Cyg_InterruptHANDLED; + return CYG_InterruptHANDLED; } -// TimeBase B ISR. Should be executing once. static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data) { - CYG_UNUSED_PARAM(CYG_ADDRWORD, data); - - CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); CYG_ASSERT (ID_TBB == data, "Wrong data!"); + + HAL_INTERRUPT_ACKNOWLEDGE(vector); + count = count*8; - HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - - count = count * 8; - -#ifdef DEBUG_PRINTFS - diag_printf( "ISR_TBB executed\n" ); -#endif - - return Cyg_InterruptHANDLED; + return CYG_InterruptHANDLED; } -void intr0_main( void ) +static cyg_uint32 +isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data) { - CYG_TEST_INIT(); + cyg_uint32 verify_value; + + CYG_UNUSED_PARAM(CYG_ADDRWORD, data); + + CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); + CYG_ASSERT (ID_PIT == data, "Wrong data!"); + + HAL_INTERRUPT_ACKNOWLEDGE(vector); -#if 0 - // The A.3 revision of the CPU I'm using at the moment generates a - // machine check exception when writing to IMM_RTCSC. Smells a - // bit like the "SIU4. Spurious External Bus Transaction Following - // PLPRCR Write." CPU errata. Have to find out for sure. Run real - // time clock interrupts on level 0 - { - // Still to do. - } -#endif - - // Run periodic timer interrupt on level 1 - { - cyg_uint16 piscr; - - // Attach pit arbiter. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1, - &hal_arbitration_isr_pit, ID_PIT, 0); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1); - - // Attach pit isr. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, - ID_PIT, 0); - HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); - - - // Set period. - HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, - (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT); - -#ifdef DEBUG_PRINTFS - diag_printf( "PIT set to %d\n", 2*PIT_PERIOD ); -#endif - // Enable. - HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - piscr |= CYGARC_REG_IMM_PISCR_PTE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); - } - - // Run timebase interrupts on level 2 - { - cyg_uint16 tbscr; - cyg_uint32 tbl; - - // Attach tb arbiter. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2, - &hal_arbitration_isr_tb, ID_TBA, 0); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2); - - // Attach tb isrs. - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, - ID_TBA, 0); - HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, - ID_TBB, 0); - HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); - HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + count++; - // Set reference A & B registers. + count_actual_table[pit_count] = count; + { + cyg_uint32 tbl; CYGARC_MFTB (TBL_R, tbl); - tbl += TB_PERIOD*3; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl); - tbl += TB_PERIOD*4; - HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl); - -#ifdef DEBUG_PRINTFS - diag_printf( "TB initial %d, !1 %d !2 %d\n", - tbl - 7*TB_PERIOD, - tbl - 4*TB_PERIOD, - tbl - 0*TB_PERIOD ); -#endif - // Enable. - HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB | - CYGARC_REG_IMM_TBSCR_TBE); - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE; - HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); - } + tbr_actual_table[pit_count] = tbl; + } - HAL_ENABLE_INTERRUPTS(); + verify_value = count_verify_table[pit_count++]; + + CYG_ASSERT (count == verify_value, "Count wrong!"); + + // End of test when count is 42. Mask interrupts and print PASS text. + if (42 <= count || 5 == pit_count) { + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); + + if(5 == pit_count) + { + if(42 != count) CYG_TEST_INFO("TB/PIT ratio does not match"); + } + + if(5 == pit_count && 42 == count) + { + CYG_TEST_PASS_FINISH("Intr 0 OK"); + } + else + { + CYG_TEST_FAIL_FINISH("Intr 0 FAILED"); + } + } + + return CYG_InterruptHANDLED; +} + +static void +intr0_main( void ) +{ + int tb_period = TB_PERIOD; + cyg_uint32 tbl; + cyg_uint16 piscr; + + // Install the PIT Interrupt arbiter + hal_arbitration_data_pit.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT; + hal_arbitration_data_pit.data = 0; + hal_arbitration_data_pit.arbiter = hal_arbitration_isr_pit; + + hal_mpc5xx_install_arbitration_isr(&hal_arbitration_data_pit); + + // attach PIT isr + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, ID_PIT, 0); + HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT); + + // Set period + HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT); + + // Enable. + HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + piscr |= CYGARC_REG_IMM_PISCR_PTE; + HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); + + // Clear any pending interrupts and enable them + HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); + + // Install the Timebase Interrupt Arbiter + hal_arbitration_data_tb.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB; + hal_arbitration_data_tb.data = 0; + hal_arbitration_data_tb.arbiter = hal_arbitration_isr_tb; + + hal_mpc5xx_install_arbitration_isr(&hal_arbitration_data_tb); + + // Attach tb isrs. + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, ID_TBA, 0); + HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, ID_TBB, 0); + HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB); + + // Set reference A & B registers. + CYGARC_MFTB (TBL_R, tbl); + tbl += tb_period*3; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl); + tbl += tb_period*4; + HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl); + + // Clear any pending interrupts and enable them + HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_SIU_TB_A); + HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_SIU_TB_B); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); + HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); - for (;;); -} + HAL_ENABLE_INTERRUPTS(); -externC void -cyg_start( void ) -{ - intr0_main(); + for(;;); } -#else // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE - externC void cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_PASS_FINISH("N/A: CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE disabled"); + intr0_main(); + CYG_TEST_PASS_FINISH("HAL Interrupt test"); } - -#endif // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE - -// EOF intr0.c Index: redboot/current/doc/redboot_installing.sgml =================================================================== RCS file: /cvs/ecos/ecos/packages/redboot/current/doc/redboot_installing.sgml,v retrieving revision 1.5 diff -u -r1.5 redboot_installing.sgml --- redboot/current/doc/redboot_installing.sgml 15 Sep 2002 21:45:31 -0000 1.5 +++ redboot/current/doc/redboot_installing.sgml 19 Nov 2002 22:23:57 -0000 @@ -4799,8 +4799,164 @@ + + +PowerPC/MPC555 Wuerz ec555 + +Overview +Wuerz ec555 + installing and testing + installing and testing + Wuerz ec555 +Redboot uses both available serial ports. The default serial port settings are +38400,8,N,1. +Management of the onboard flash is supported. The supplied version of redboot does not conflict + with the macraigor wiggler BDM debugger. It does include stubs for serial debugging as wel. Thread + aware debugging is supported, as are command line editing. +The following Redboot configurations are supported: + + + + + Configuration + Mode + Description + File + + + + + ROM + [ROM] + RedBoot running from the MPC555's on-chip flash. + redboot_ROM.ecm + + + + + + + + Initial installation + Program the ROM Redboot image to the MPC555's on-chip flash using either the supplied monitor + or a BDM based programmer. Instructions on how to use the supplied monitor can be found in the + ec555mon manual that ships with the board. Do not forget to program the reset configuration word + with the value zero and untie the RTSCONF pin from ground to force the board to boot from the + internal flash rather than from the external one. + + + + + Memory Maps + Redboot sets up the following memory map on the ec555 board. +Physical Address Range Description +----------------------- ----------- +0x000000 - 0x06ffff Internal flash (ocupied by redboot) +0x3f9800 - 0x3fffff Internal ram (reserved for virtual vector table) +0x400000 - 0x4fffff DRAM (available to the application) +0x800000 - 0xa00000 FLASH (AM29LV800) (available to the application) + + + + +Rebuilding RedBoot + +These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +: + +export TARGET=ec555 +export ARCH_DIR=powerpc +export PLATFORM_DIR=ec555 + + + +The names of configuration files are listed above with the +description of the associated modes. + + + + + + +PowerPC/MPC555 Axiom CME555 + +Overview +Axiom ec555 + installing and testing + installing and testing + Axiom ec555 +Redboot uses both available serial ports. The default serial port settings are +38400,8,N,1. +Management of the onboard flash is supported. The supplied version of redboot does not conflict + with the macraigor wiggler BDM debugger. It does include stubs for serial debugging as wel. Thread + aware debugging is supported, as are command line editing. + +The following Redboot configurations are supported: + + + + + Configuration + Mode + Description + File + + + + + ROM + [ROM] + RedBoot running from the MPC555's on-chip flash. + redboot_ROM.ecm + + + + + + + + + Initial installation + Program the ROM Redboot image to the MPC555's on-chip flash using either the supplied monitor + or a BDM based programmer. Instructions on how to use the supplied monitor are shipped with the board. + Set the M-SEL jumper to position 3, FLASH-SEL to 2 and RAM-SEL to 1 afterwards. Mode-SW 1 must be set to + 01000000b and Mode-SW 2 to 00010000b to make the board boot from the internal flash. + + + + + Memory Maps + Redboot sets up the following memory map on the ec555 board. +Physical Address Range Description +----------------------- ----------- +0x000000 - 0x06ffff Internal flash (ocupied by redboot) +0x3f9800 - 0x3fffff Internal ram (reserved for virtual vector table) +0x400000 - 0x47ffff DRAM (available to the application) +0x800000 - 0x87ffff FLASH (AM29LV200) (available to the application) + + + + +Rebuilding RedBoot + +These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +: + +export TARGET=cme555 +export ARCH_DIR=powerpc +export PLATFORM_DIR=cme555 + + + +The names of configuration files are listed above with the +description of the associated modes. + + +