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CSB281 - Lots of improvements
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 03 Jan 2003 20:39:22 -0700
- Subject: CSB281 - Lots of improvements
Now running in ROMRAM mode (RedBoot), plus full caches and interrupts.
Index: hal/powerpc/csb281/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/ChangeLog,v
retrieving revision 1.1
diff -u -5 -p -r1.1 ChangeLog
--- hal/powerpc/csb281/current/ChangeLog 24 Dec 2002 16:00:48 -0000 1.1
+++ hal/powerpc/csb281/current/ChangeLog 3 Jan 2003 17:49:47 -0000
@@ -1,5 +1,29 @@
+2003-01-03 Gary Thomas <gary@mlbassoc.com>
+
+ * src/hal_diag.c (cyg_hal_plf_serial_error): New function - fixed
+ some random [timing?] problems with getc().
+
+ * src/csb281.S: Fix ROMRAM startup. Minor cleanups.
+
+ * misc/redboot_ROM.ecm:
+ * misc/redboot_RAM.ecm: Update.
+
+ * include/pkgconf/mlt_powerpc_csb281_romram.mlt:
+ * include/pkgconf/mlt_powerpc_csb281_romram.ldi:
+ * include/pkgconf/mlt_powerpc_csb281_romram.h: Fix RAM size.
+
+ * src/hal_aux.c:
+ * include/plf_io.h: Define uncached, separately mapped, PCI space.
+
+2003-01-02 Gary Thomas <gary@mlbassoc.com>
+
+ * src/hal_aux.c (hal_platform_init): Need to clear all interrupt
+ sources - very manually - reset doesn't do this.
+
+ * include/platform.inc: Don't run EOI cycle for spurious interrupts.
+
2002-12-24 Gary Thomas <gary@mlbassoc.com>
* src/redboot_linux_exec.c:
* src/hal_diag.c:
* src/hal_aux.c:
Index: hal/powerpc/csb281/current/include/platform.inc
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/include/platform.inc,v
retrieving revision 1.1
diff -u -5 -p -r1.1 platform.inc
--- hal/powerpc/csb281/current/include/platform.inc 24 Dec 2002 16:00:49 -0000 1.1
+++ hal/powerpc/csb281/current/include/platform.inc 2 Jan 2003 20:53:19 -0000
@@ -9,11 +9,11 @@
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -66,14 +66,14 @@
rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
beq 0f # done if decrementer (vec 0)
lwi \dreg,_CSB281_EPIC_IACK # if external, get vector
li r0,0
lwbrx \dreg,r0,\dreg # EPIC is little endian!
- lwi r3,_CSB281_EPIC_EOI # clear interrupt?
- stw r0,0(r3)
cmpi 0,\dreg,0xFF # spurious interrupt?
beq restore_state
+ lwi r3,_CSB281_EPIC_EOI # clear interrupt?
+ stw r0,0(r3)
0: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
slwi \dreg,\dreg,2 # convert to byte offset.
.endm
#define CYGPKG_HAL_POWERPC_INTC_DEFINED
Index: hal/powerpc/csb281/current/include/plf_io.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/include/plf_io.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 plf_io.h
--- hal/powerpc/csb281/current/include/plf_io.h 24 Dec 2002 16:00:49 -0000 1.1
+++ hal/powerpc/csb281/current/include/plf_io.h 3 Jan 2003 14:50:42 -0000
@@ -10,11 +10,11 @@
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -63,12 +63,14 @@
//-----------------------------------------------------------------------------
//
// PCI support
//
-#define CYGARC_PHYSICAL_ADDRESS(x) (x)
-#define CYGARC_UNCACHED_ADDRESS(x) (x)
+#define _EOM (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE)
+#define _PCI_MAP 0x80000000
+#define CYGARC_PHYSICAL_ADDRESS(x) (((x) >= _PCI_MAP) ? ((x) & 0x0FFFFFFF) : (x))
+#define CYGARC_UNCACHED_ADDRESS(x) ((x) + _PCI_MAP)
// Restrict device [slot] space
#define CYG_PCI_MAX_BUS 1 // Only one BUS
#define CYG_PCI_MIN_DEV 11 // Slots start at 11
#define CYG_PCI_MAX_DEV 14 // ... and end at 13
@@ -82,12 +84,12 @@
// This is where the PCI spaces are mapped in the CPU's address space.
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0 // Address maps are 1-1
#define HAL_PCI_PHYSICAL_IO_BASE 0
-// [hard-wired] shared memory segment
-#define CYGMEM_SECTION_pci_window CYGMEM_REGION_ram_SIZE // "end" of RAM
+// shared memory segment
+#define CYGMEM_SECTION_pci_window CYGARC_UNCACHED_ADDRESS(CYGMEM_REGION_ram_SIZE)
#define CYGMEM_SECTION_pci_window_SIZE 0x00100000
// Initialize the PCI environment
externC void _csb281_pci_init(void);
#define HAL_PCI_INIT() \
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 mlt_powerpc_csb281_romram.h
--- hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h 24 Dec 2002 16:00:50 -0000 1.1
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h 3 Jan 2003 17:34:42 -0000
@@ -6,12 +6,12 @@
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
#endif
#define CYGMEM_REGION_ram (0)
-#define CYGMEM_REGION_ram_SIZE (0x800000)
+#define CYGMEM_REGION_ram_SIZE (0x1F00000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
-#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x1F00000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi,v
retrieving revision 1.1
diff -u -5 -p -r1.1 mlt_powerpc_csb281_romram.ldi
--- hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi 24 Dec 2002 16:00:50 -0000 1.1
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi 3 Jan 2003 17:34:43 -0000
@@ -4,11 +4,11 @@
#include <cyg/infra/cyg_type.inc>
MEMORY
{
- ram : ORIGIN = 0, LENGTH = 0x800000
+ ram : ORIGIN = 0, LENGTH = 0x1F00000
}
SECTIONS
{
SECTIONS_BEGIN
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt,v
retrieving revision 1.1
diff -u -5 -p -r1.1 mlt_powerpc_csb281_romram.mlt
--- hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt 24 Dec 2002 16:00:50 -0000 1.1
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt 3 Jan 2003 17:34:42 -0000
@@ -1,7 +1,7 @@
version 0
-region ram 0 800000 0 !
+region ram 0 1f00000 0 !
section vectors 0 1 0 1 1 0 1 0 0 0 !
section text 0 1 0 1 1 1 1 1 3400 3400 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 fixup fixup !
Index: hal/powerpc/csb281/current/misc/redboot_RAM.ecm
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/misc/redboot_RAM.ecm,v
retrieving revision 1.1
diff -u -5 -p -r1.1 redboot_RAM.ecm
--- hal/powerpc/csb281/current/misc/redboot_RAM.ecm 24 Dec 2002 16:00:50 -0000 1.1
+++ hal/powerpc/csb281/current/misc/redboot_RAM.ecm 3 Jan 2003 17:40:42 -0000
@@ -23,10 +23,11 @@ cdl_configuration eCos {
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
package -template CYGPKG_LIBC_STRING current ;
package -template CYGPKG_NS_DNS current ;
+ package -template CYGPKG_CRC current ;
package CYGPKG_IO_FLASH current ;
package CYGPKG_IO_ETH_DRIVERS current ;
};
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
@@ -35,10 +36,14 @@ cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS
cdl_component CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA {
user_value 1
};
+cdl_option CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER {
+ user_value 0 0
+};
+
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
@@ -47,12 +52,12 @@ cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
-cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
- user_value 0
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ user_value 1
};
cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
user_value 1
};
Index: hal/powerpc/csb281/current/misc/redboot_ROM.ecm
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/misc/redboot_ROM.ecm,v
retrieving revision 1.1
diff -u -5 -p -r1.1 redboot_ROM.ecm
--- hal/powerpc/csb281/current/misc/redboot_ROM.ecm 24 Dec 2002 16:00:50 -0000 1.1
+++ hal/powerpc/csb281/current/misc/redboot_ROM.ecm 3 Jan 2003 17:40:59 -0000
@@ -23,10 +23,11 @@ cdl_configuration eCos {
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
package -template CYGPKG_LIBC_STRING current ;
package -template CYGPKG_NS_DNS current ;
+ package -template CYGPKG_CRC current ;
package CYGPKG_IO_FLASH current ;
package CYGPKG_IO_ETH_DRIVERS current ;
};
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
@@ -47,11 +48,11 @@ cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
-cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
user_value 0
};
cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
user_value 1
Index: hal/powerpc/csb281/current/misc/redboot_ROMRAM.ecm
===================================================================
RCS file: hal/powerpc/csb281/current/misc/redboot_ROMRAM.ecm
diff -N hal/powerpc/csb281/current/misc/redboot_ROMRAM.ecm
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/misc/redboot_ROMRAM.ecm 3 Jan 2003 17:40:19 -0000
@@ -0,0 +1,121 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware csb281 ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_POWERPC current ;
+ package -hardware CYGPKG_HAL_POWERPC_PPC60x current ;
+ package -hardware CYGPKG_HAL_POWERPC_CSB281 current ;
+ package -hardware CYGPKG_DEVS_FLASH_STRATA current ;
+ package -hardware CYGPKG_DEVS_FLASH_CSB281 current ;
+ package -hardware CYGPKG_IO_PCI current ;
+ package -hardware CYGPKG_DEVS_ETH_CSB281 current ;
+ package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_NS_DNS current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_IO_FLASH current ;
+ package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA {
+ user_value 1
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+ user_value 1
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+ user_value 1
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+ user_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ user_value 0x00040000
+};
+
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+ user_value 0x01F00000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+
Index: hal/powerpc/csb281/current/src/csb281.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/src/csb281.S,v
retrieving revision 1.1
diff -u -5 -p -r1.1 csb281.S
--- hal/powerpc/csb281/current/src/csb281.S 24 Dec 2002 16:00:51 -0000 1.1
+++ hal/powerpc/csb281/current/src/csb281.S 3 Jan 2003 17:22:47 -0000
@@ -7,11 +7,11 @@
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -81,60 +81,10 @@ FUNC_START(_led)
FUNC_END(_led)
#------------------------------------------------------------------------------
FUNC_START( hal_hardware_init )
-
-#if 0 // Seem to be 860 specific
-
-#define CACHE_UNLOCKALL 0x0a00
-#define CACHE_DISABLE 0x0400
-#define CACHE_INVALIDATEALL 0x0c00
-#define CACHE_ENABLE 0x0200
-#define CACHE_ENABLEBIT 0x8000
-
-#define CACHE_FORCEWRITETHROUGH 0x0100
-#define CACHE_NOWRITETHROUGH 0x0300
-#define CACHE_CLEAR_LE_SWAP 0x0700
-
- # DATA CACHE
- mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
- lis r3,CACHE_UNLOCKALL
- sync
- mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
-
- lis r3,CACHE_INVALIDATEALL
- sync
- mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
-
- lis r3,CACHE_DISABLE
- sync
- mtspr CYGARC_REG_DC_CST,r3 /* disable */
-
- lis r3,CACHE_FORCEWRITETHROUGH
- sync
- mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
-
- lis r3,CACHE_CLEAR_LE_SWAP
- sync
- mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
- /* (dunno what this is, but it sounds like a bad thing) */
-
- # INSTRUCTION CACHE (no writeback modes)
- mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
- lis r3,CACHE_UNLOCKALL
- mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
- isync
- lis r3,CACHE_INVALIDATEALL
- mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
- isync
- lis r3,CACHE_DISABLE
- mtspr CYGARC_REG_IC_CST,r3 /* disable */
- isync
-
- sync
-#endif
// Basic hardware initialization
mflr r31
bl 10f // Gets position independent address of table
HW_init:
@@ -176,12 +126,12 @@ HW_init:
mtdec r2
#ifdef CYG_HAL_STARTUP_ROMRAM
// Copy image from ROM to RAM
mflr r3
- lwi r4,0xFFF00000
- lwi r5,0x000FFFFF // ROM/FLASH base
+ lwi r4,0xFF000000
+ lwi r5,0x00FFFFFF // ROM/FLASH base
and r3,r3,r5 // segment relative
lwi r6,_hal_hardware_init_done
mtlr r6
sub r6,r3,r6 // Absolute address
add r6,r6,r4 // FLASH address
Index: hal/powerpc/csb281/current/src/hal_aux.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/src/hal_aux.c,v
retrieving revision 1.1
diff -u -5 -p -r1.1 hal_aux.c
--- hal/powerpc/csb281/current/src/hal_aux.c 24 Dec 2002 16:00:51 -0000 1.1
+++ hal/powerpc/csb281/current/src/hal_aux.c 3 Jan 2003 14:23:03 -0000
@@ -7,11 +7,11 @@
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -70,20 +70,24 @@
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
// Mapping for the Cogent CSB281 development boards
CYGARC_MEMDESC_NOCACHE( 0x70000000, 0x10000000 ), // FLASH region, LCD, PS/2
CYGARC_MEMDESC_NOCACHE( 0xf0000000, 0x10000000 ), // PCI space, LEDS, control
CYGARC_MEMDESC_CACHE( CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
+// Main memory, mapped non-cacheable for PCI use
+ CYGARC_MEMDESC_NOCACHE_PA(CYGMEM_SECTION_pci_window,
+ CYGARC_PHYSICAL_ADDRESS(CYGMEM_SECTION_pci_window),
+ CYGMEM_SECTION_pci_window_SIZE),
CYGARC_MEMDESC_TABLE_END
};
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
- cyg_uint32 bcsr, gcr, frr, eicr;
+ cyg_uint32 bcsr, gcr, frr, eicr, iack;
int vec;
// Initialize I/O interfaces
hal_if_init();
// Reset interrupt controller/state
@@ -99,17 +103,24 @@ hal_platform_init(void)
HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
}
+ vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
+ while (vec-- > 0) {
+ HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
+ HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
+ }
HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Reset peripherals
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
_csb281_i2c_init();
_csb281_fs6377_init();
+#endif
_csb281_pci_init();
}
//--------------------------------------------------------------------------
// Interrupt support
Index: hal/powerpc/csb281/current/src/hal_diag.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/csb281/current/src/hal_diag.c,v
retrieving revision 1.1
diff -u -5 -p -r1.1 hal_diag.c
--- hal/powerpc/csb281/current/src/hal_diag.c 24 Dec 2002 16:00:51 -0000 1.1
+++ hal/powerpc/csb281/current/src/hal_diag.c 3 Jan 2003 17:49:49 -0000
@@ -7,11 +7,11 @@
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -57,10 +57,11 @@
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_misc.h> // cyg_hal_is_break()
#include <cyg/hal/hal_intr.h> // Interrupt macros
#include <cyg/hal/drv_api.h>
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#include <cyg/hal/hal_stub.h> // hal_output_gdb_string
@@ -100,10 +101,11 @@
#define CYG_DEV_SERIAL_MCR_A 0x04
#define CYG_DEV_SERIAL_MCR_B 0x04
#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
+#define CYG_DEV_SERIAL_DCR 0x11 // device control (UART vs DUART)
// The interrupt enable register bits.
#define SIO_IER_ERDAI 0x01 // enable received data available irq
#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
#define SIO_IER_ELSI 0x04 // enable receiver line status irq
@@ -144,13 +146,16 @@
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
// The FIFO control register
-#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
-#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
-#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
+#define SIO_FCR_FEN 0x01 // enable xmit and rcvr fifos
+#define SIO_FCR_RFR 0x02 // clear RCVR FIFO
+#define SIO_FCR_TFR 0x04 // clear XMIT FIFO
+
+// DUART control
+#define SIO_DCR_SDM 0x01 // Special DUART mode
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
@@ -161,18 +166,20 @@ typedef struct {
//-----------------------------------------------------------------------------
static void
init_serial_channel(const channel_data_t* __ch_data)
{
cyg_uint8* base = __ch_data->base;
- cyg_uint8 lcr;
+ cyg_uint8 lcr, iir;
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, 0);
// Disable and clear FIFOs (need to enable to clear).
- HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
- (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
- HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0);
+ HAL_READ_UINT8(base+CYG_DEV_SERIAL_IIR, iir);
+ if ((iir & 0xC0) == 0) {
+ HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, (SIO_FCR_FEN | SIO_FCR_RFR | SIO_FCR_TFR));
+ HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0);
+ }
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
// Set speed to 38400.
@@ -186,37 +193,34 @@ init_serial_channel(const channel_data_t
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM,
CYG_DEV_SERIAL_RS232_T1_VALUE_B38400);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
-#if 0 // Necessary?
- {
- // Special initialization for ST16C552 on CMA102
- cyg_uint8 mcr;
-
- HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr);
- mcr |= 8;
- HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr);
-
- HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr);
- mcr |= 8;
- HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr);
- }
-#endif
+ HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DCR, SIO_DCR_SDM);
// Enable FIFOs (and clear them).
- HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
- (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
+ if ((iir & 0xC0) == 0) {
+ HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, (SIO_FCR_FEN | SIO_FCR_RFR | SIO_FCR_TFR));
+ }
+}
+
+static void
+cyg_hal_plf_serial_error(void *__ch_data, cyg_uint8 lsr)
+{
+ // Ignore?
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
+ if ((lsr & SIO_LSR_ERR) != 0) {
+ cyg_hal_plf_serial_error(__ch_data, lsr);
+ }
if ((lsr & SIO_LSR_DR) == 0)
return false;
HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
--
------------------------------------------------------------
Gary Thomas |
MLB Associates | Consulting for the
+1 (970) 229-1963 | Embedded world
http://www.mlbassoc.com/ |
email: <gary@mlbassoc.com> |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------