Index: packages/hal/arm/arm9/innovator/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/ChangeLog,v retrieving revision 1.2 diff -u -5 -p -r1.2 ChangeLog --- packages/hal/arm/arm9/innovator/current/ChangeLog 13 Feb 2003 15:27:37 -0000 1.2 +++ packages/hal/arm/arm9/innovator/current/ChangeLog 15 Apr 2003 19:19:50 -0000 @@ -1,5 +1,29 @@ +2003-04-15 Patrick Doyle + + * cdl/hal_arm_arm9_innovator.cdl: Added configuration items to + support the real time clock. + + * include/hal_platform_ints.h: Added support for interrupt + controller. + + * include/hal_platform_setup.h: Miscellaneous cleanups. Some + related to enabling the cache, some related to documenation, etc... + + * include/innovator.h: Moved most of this into (the newly defined) + omap1510.h file. + + * misc/redboot_SRAM.ecm: Enable the caches on startup, set + 'CYGBLD_REDBOOT_MIN_IMAGE_SIZE' to match the other .ecm files. + + * src/innovator_misc.c: Added interrupt and RTC support. Changed + 'hal_delay_us()' to use timer2 instead of timer1 since timer1 is + used as the RTC. + + * src/redboot_cmds.c (do_init_dsp): Added the "init_dsp" command. + The rest of this file is currently commented out. + 2003-02-12 Patrick Doyle * src/innovator_misc.c: Replaced explicit prototype of memset with #include . Index: packages/hal/arm/arm9/innovator/current/cdl/hal_arm_arm9_innovator.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/cdl/hal_arm_arm9_innovator.cdl,v retrieving revision 1.2 diff -u -5 -p -r1.2 hal_arm_arm9_innovator.cdl --- packages/hal/arm/arm9/innovator/current/cdl/hal_arm_arm9_innovator.cdl 13 Feb 2003 01:01:09 -0000 1.2 +++ packages/hal/arm/arm9/innovator/current/cdl/hal_arm_arm9_innovator.cdl 15 Apr 2003 19:19:50 -0000 @@ -106,65 +106,61 @@ cdl_package CYGPKG_HAL_ARM_ARM9_INNOVATO The SRAM option is used to place the ROM image in internal SRAM. It may be used in order to test startup code without burning the code into FLASH first." } } - # Both PLLs are in bypass mode on startup. - # FIXME: Add proper configury - cdl_option CYGNUM_HAL_ARM_INNOVATOR_CPU_CLOCK { - display "CPU bus speed" + cdl_option CYGNUM_HAL_ARM_INNOVATOR_MPUTIM_CLOCK { + display "MPU Timer clock speed" flavor data - calculated { 60000000 } + calculated { 12000000 } description " - This is the actual CPU operating frequency. Someday you - might be able to change this here." + This is the speed of the clock that drives the three MPU + timers. Currently, it is hardwired at 12MHz (implying that + the clock source is the 12MHz CLKIN signal). Someday we + might add a CDL option to select CK_GEN1 as the clock + source for the timers, but we will probably also want to + add items for configuring CK_GEN1 as well at that time." } -# cdl_option CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK { -# display "Peripheral bus speed" -# flavor data -# calculated { CYGNUM_HAL_ARM_INNOVATOR_CPU_CLOCK / 2 } -# description " -# This is the peripheral bus operating frequency -# (Traffic Controller)." -# } -# -# cdl_option CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE { -# display "Timer prescale" -# flavor data -# legal_values 0 to 255 -# default_value 16 -# description " -# This is the prescale value used on the clock used to drive -# the kernel counter. Note that some parts of the code may fail -# if this is changed due to over/underflows of expressions." -# } -# -# # Real-time clock/counter specifics -# cdl_component CYGNUM_HAL_RTC_CONSTANTS { -# display "Real-time clock constants. WARNING -- the Real Time Clock is not fully supported (if at all) yet." -# flavor none -# no_define -# -# cdl_option CYGNUM_HAL_RTC_NUMERATOR { -# display "Real-time clock numerator" -# flavor data -# calculated 1000000000 -# } -# cdl_option CYGNUM_HAL_RTC_DENOMINATOR { -# display "Real-time clock denominator" -# flavor data -# calculated 100 -# } -# cdl_option CYGNUM_HAL_RTC_PERIOD { -# display "Real-time clock period" -# flavor data -# calculated 1 -## calculated (CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/(CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE*CYGNUM_HAL_RTC_DENOMINATOR))-1 -# } -# } -# + cdl_option CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE_LOG { + display "(Log, base 2 of the) Timer prescale" + flavor data + legal_values 1 to 8 + default_value 1 + description " + This specifies the prescale value used on the clock used to drive + the kernel counter. Note that some parts of the code may fail + if this is changed due to over/underflows of expressions. + The actual prescale value is + 2^CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE_LOG" + } + + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated CYGNUM_HAL_ARM_INNOVATOR_MPUTIM_CLOCK/((1< // These are interrupts on the Innovator -// TBD -#define CYGNUM_HAL_ISR_COUNT 1 // No interrupt support defined yet. +// (interrupts 0 and 1 are the FIQ and IRQ outputs of the 2nd level +// interrupt handler) +#define CYGNUM_HAL_INTERRUPT_USB_NIRQ 2 +#define CYGNUM_HAL_INTERRUPT_USB_SOF_NIRQ 3 +#define CYGNUM_HAL_INTERRUPT_MCBSP2_TX 4 +#define CYGNUM_HAL_INTERRUPT_MCBSP2_RX 5 +#define CYGNUM_HAL_INTERRUPT_CAMERA 6 +#define CYGNUM_HAL_INTERRUPT_reserved07 7 +#define CYGNUM_HAL_INTERRUPT_reserved08 8 +#define CYGNUM_HAL_INTERRUPT_ABORT 9 +#define CYGNUM_HAL_INTERRUPT_DSP_MAILBOX1 10 +#define CYGNUM_HAL_INTERRUPT_DSP_MAILBOX2 11 +#define CYGNUM_HAL_INTERRUPT_HSP_MAILBOX 12 +#define CYGNUM_HAL_INTERRUPT_PERIPERHAL_BRIDGE_PRIVATE 13 +#define CYGNUM_HAL_INTERRUPT_GPIO 14 +#define CYGNUM_HAL_INTERRUPT_UART3 15 +#define CYGNUM_HAL_INTERRUPT_TIMER3 16 +#define CYGNUM_HAL_INTERRUPT_LB_MMU 17 +#define CYGNUM_HAL_INTERRUPT_HIGH_SPEED_BUS_MMU 18 +#define CYGNUM_HAL_INTERRUPT_DMA_CH0_6 19 +#define CYGNUM_HAL_INTERRUPT_DMA_CH1_7 20 +#define CYGNUM_HAL_INTERRUPT_DMA_CH2_8 21 +#define CYGNUM_HAL_INTERRUPT_DMA_CH3 22 +#define CYGNUM_HAL_INTERRUPT_DMA_CH4 23 +#define CYGNUM_HAL_INTERRUPT_DMA_CH5 24 +#define CYGNUM_HAL_INTERRUPT_DMA_CH_LCD 25 +#define CYGNUM_HAL_INTERRUPT_TIMER1 26 +#define CYGNUM_HAL_INTERRUPT_WD_TIMER 27 +#define CYGNUM_HAL_INTERRUPT_PERIPHERAL_BRIDGE_PUBLIC 28 +#define CYGNUM_HAL_INTERRUPT_LOCAL_BUS_IF 29 +#define CYGNUM_HAL_INTERRUPT_TIMER2 30 +#define CYGNUM_HAL_INTERRUPT_LCD_CTRL 31 -// Placeholders -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX 0 -// The vector used by the Real time clock -- fake, for now -#define CYGNUM_HAL_INTERRUPT_RTC 0 +// Note that interrupt vectors 32..63 are mapped into IRQ 0 and 1 of the +// level 1 interrupt handler. +#define CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK 32 + +#define CYGNUM_HAL_INTERRUPT_HW_ERRORS 32 +#define CYGNUM_HAL_INTERRUPT_KEYBOARD 33 +#define CYGNUM_HAL_INTERRUPT_MICROWIRE_TX 34 +#define CYGNUM_HAL_INTERRUPT_MICROWIRE_RX 35 +#define CYGNUM_HAL_INTERRUPT_I2C 36 +#define CYGNUM_HAL_INTERRUPT_MPUIO 37 +#define CYGNUM_HAL_INTERRUPT_reserved37 38 +#define CYGNUM_HAL_INTERRUPT_reserved38 39 +#define CYGNUM_HAL_INTERRUPT_reserved39 40 +#define CYGNUM_HAL_INTERRUPT_reserved40 41 +#define CYGNUM_HAL_INTERRUPT_MCBSP3_TX 42 +#define CYGNUM_HAL_INTERRUPT_MCBSP3_RX 43 +#define CYGNUM_HAL_INTERRUPT_MCBSP1_TX 44 +#define CYGNUM_HAL_INTERRUPT_MCBSP1_RX 45 +#define CYGNUM_HAL_INTERRUPT_UART1 46 +#define CYGNUM_HAL_INTERRUPT_UART2 47 +#define CYGNUM_HAL_INTERRUPT_BT_ULAW_MCSI1_TX 48 +#define CYGNUM_HAL_INTERRUPT_BT_ULAW_MCSI1_RX 49 +#define CYGNUM_HAL_INTERRUPT_BT_ULAW_MCSI1_FRAME_ERR 50 +#define CYGNUM_HAL_INTERRUPT_COMM_ULAW_MCSI2_TX 51 +#define CYGNUM_HAL_INTERRUPT_COMM_ULAW_MCSI2_RX 52 +#define CYGNUM_HAL_INTERRUPT_COMM_ULAW_MCSI2_FRAME_ERR 53 +#define CYGNUM_HAL_INTERRUPT_32KHZ_TIMER 54 +#define CYGNUM_HAL_INTERRUPT_MMC 55 +#define CYGNUM_HAL_INTERRUPT_32K_GAUGING 56 +#define CYGNUM_HAL_INTERRUPT_reserved57 57 +#define CYGNUM_HAL_INTERRUPT_reserved58 58 +#define CYGNUM_HAL_INTERRUPT_reserved59 59 +#define CYGNUM_HAL_INTERRUPT_DSP_MMU 60 +#define CYGNUM_HAL_INTERRUPT_USB_GEN1 61 +#define CYGNUM_HAL_INTERRUPT_USB_SBI1 62 +#define CYGNUM_HAL_INTERRUPT_COMM_SPI_RX_OVERFLOW 63 + + +#define CYGNUM_HAL_ISR_MIN 2 +#define CYGNUM_HAL_ISR_MAX 63 + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) + +#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_INTERRUPT_TIMER1) //---------------------------------------------------------------------------- // Reset. // Enable the watchdog timer to force a reset -#define HAL_PLATFORM_RESET() CYG_MACRO_START \ - cyg_uint16 tmp; \ - HAL_READ_UINT16(CLKM_ARM_IDLECT2, tmp); \ - HAL_WRITE_UINT16(CLKM_ARM_IDLECT2, tmp | 1); \ - HAL_DELAY_US(4); \ - HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ - HAL_DELAY_US(4); \ - HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ +#define HAL_PLATFORM_RESET() CYG_MACRO_START \ + cyg_uint16 tmp; \ + HAL_READ_UINT16(CLKM_ARM_IDLECT2, tmp); \ + HAL_WRITE_UINT16(CLKM_ARM_IDLECT2, tmp | 1); \ + /* I read somewhere that you have to wait up to 4 Microseconds for */ \ + /* playing with the watchdog timer... I should double check that */ \ + /* someday, but since all we are doing here is waiting for the */ \ + /* processor to reset, who cares? */ \ + HAL_DELAY_US(4); \ + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ + HAL_DELAY_US(4); \ + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ + for(;;); /* wait for it */ \ CYG_MACRO_END #define HAL_PLATFORM_RESET_ENTRY 0x10000000 #endif // CYGONCE_HAL_PLATFORM_INTS_H Index: packages/hal/arm/arm9/innovator/current/include/hal_platform_setup.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/include/hal_platform_setup.h,v retrieving revision 1.2 diff -u -5 -p -r1.2 hal_platform_setup.h --- packages/hal/arm/arm9/innovator/current/include/hal_platform_setup.h 13 Feb 2003 01:01:09 -0000 1.2 +++ packages/hal/arm/arm9/innovator/current/include/hal_platform_setup.h 15 Apr 2003 19:19:50 -0000 @@ -80,14 +80,11 @@ // new test version of RedBoot to SRAM (configured with CYGPRI_HAL_ROM_MLT // set to SRAM) (more on that later), press and hold the reset button, // and see if the new startup code works. // // Now for some notes about this -// 1) I am guessing about the "2 seconds" part. If you press and hold -// the reset button long enough, the FPGA triggers a power-on-reset. -// -// 2) In order to test the SRAM version of RedBoot, import the +// 1) In order to test the SRAM version of RedBoot, import the // redboot_SRAM.ecm file (instead of redboot_RAM.ecm or redboot_ROM.ecm) // and build RedBoot. If you already have RedBoot in FLASH, you can // use that to load redboot.bin with a base address of 0x20000000. // You will be prompted with a "Gee, I don't think 0x20000000 is // a valid address in RAM, are you sure you want to do this?" message. @@ -97,11 +94,11 @@ // // You can also use the "sloader" application (loaded via // Code Composer Studio) to to load the S-Record file for the SRAM // version of RedBoot. // -// 3) I may have seen a case where the code tested fine in SRAM, but didn't +// 2) I may have seen a case where the code tested fine in SRAM, but didn't // work when I placed it in FLASH. But other things could have been // going on. #ifdef CYGPRI_HAL_ROM_MLT_SRAM #define PLATFORM_PREAMBLE _platform_preamble @@ -158,200 +155,10 @@ moveq pc,r2 FAKE_LED_MACRO_SETUP FAKE_LED_MACRO(1) - //#define PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT -#ifdef PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT - // This is the version of _platform_setup adapted from the contents - // of the GEL script shipped with Code Composer Studio - - // This is all stolen from the ipaq setup - - // Make sure MMU is OFF - mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading - add r2,r0,#0x2000 // cache from the internal memory bank -123: ldr r1,[r0],#16 - cmp r0, r2 - bne 123b - mov r0,#0 - mov r1,#0x0070 // MMU Control System bit - mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache - mcr p15,0,r0,c8,c7,0 // Flush ID TLBs - mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer - mcr p15,0,r0,c7,c10,4 // Drain write buffer - mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping - mcr p15,0,r1,c1,c0,0 // Write MMU control register - nop; nop; nop; nop - - mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) - msr cpsr,r0 - - // The rest of this is stolen from "init.c" in the sloader program. - // FIXME -- add configury - // Set up DPLL1: - // (reserved) 00 - // IOB = 1 Initialize on break 1 - // (reserved) 0 - // PLL_MULT = 5 60 MHz clock 0010 1 - // PLL_DIV = 00: CLKOUT = CLKREF 00 - // PLL_ENABLE = 1 Enable DPLL 1 - // BYPASS_DIV = 00: CLKOUT = CLKREF 00 - // (read only) 00 - // - // 0x2290: 0010 0010 1001 0000 - // - - ldr r1,=DPLL1_BASE - ldr r2,=0x2290 - str r2,[r1,#_DPLL_CTL_REG] - /* Wait for lock */ -1: ldr r2,[r1,#_DPLL_CTL_REG] - and r2,r2,#1 - cmp r2,#1 - bne 1b - - /* memif_init() */ - /* Configure ARM9 Memory Interface */ - /* Set up CS0 for memory & bus size of 16 bits, asynchronous read, - * 3 wait states, and a divide by 2 clock. - * Set up CS1, CS2, & CS3 the same way, except with 1 wait state. - */ -/* - TC_EMIFS_CS0_CONFIG = 0x00003339; - TC_EMIFS_CS1_CONFIG = 0x00001139; - TC_EMIFS_CS2_CONFIG = 0x00001139; - TC_EMIFS_CS3_CONFIG = 0x00001139; -*/ - ldr r1,=TC_BASE - ldr r2,=0x3339 - str r2,[r1,#0x10] - ldr r2,=0x1149 - str r2,[r1,#0x14] - ldr r2,=0x1139 - str r2,[r1,#0x18] - str r2,[r1,#0x1c] - - /* Configure the SDRAM */ - /* EMIFF (nCS4) configuration */ - /* TC_EMIFF_SDRAM_CONFIG = 0x000100F4; */ - /* MRS (nCS4) initialization */ - /* TC_EMIFF_MRS = 0x00000037; */ - ldr r2,=0x000100F4 - str r2,[r1,#0x20] - ldr r2,=0x00000037 - str r2,[r1,#0x24] - - /* Disable ARM9 Watchdog Timer by writing the special sequence to it */ -/* - WATCHDOG_TIMER_MODE = 0x00F5; - WATCHDOG_TIMER_MODE = 0x00A0; -*/ - ldr r1,=WATCHDOG_BASE - ldr r2,=0xF5 - strh r2,[r1,#0x08] - ldr r2,=0xA0 - strh r2,[r1,#0x08] - /* Select the 12MHz oscillator for the frequency reference for the - * internal timers. I am doing this today (12/19/02) to simplify my - * life -- This way, I don't care what the clock rate of the core is. - */ - ldr r1,=CLKM_BASE - ldrh r2,[r1,#0x00] // ARM_CKCTL - bic r2,r2,#0x1000 // Set ARM_TIMXO = 0 - strh r2,[r1,#0x00] - - /* Enable the MPUXOR_CK by: - * "MPUXOR_CK ... is derived from CK_REF ... and is enabled by EN_XORPCK" - * - * EN_XORPCK is bit 1 of ARM_IDLECT2 - */ -/* - CLKM_ARM_IDLECT2 |= 0x0002; -*/ - ldrh r2,[r1,#0x08] - orr r2,r2,#0x0082 // Bits 7 (EN_TIMCK) and 1 (EN_XORPCK) - strh r2,[r1,#0x08] - - /* Then set the PER_EN bit to 1 - * - * PER_EN is bit 0 of ARM_RSTCT2 - */ -/* - CLKM_ARM_RSTCT2 |= 0x0001; -*/ - ldrh r2,[r1,#0x14] - orr r2,r2,#0x0001 - strh r2,[r1,#0x14] - - /* Set the "BT_UART_GATING" bit to 1 in the FUNC_MUX_CTRL_0 register. - * This enables the TX1 and RTS1 pins. - */ -/* - CONFIG_FUNC_MUX_CTRL_0 |= BIT_25; -*/ - ldr r1,=CONFIG_BASE - ldr r3,=0x02000000 - ldr r2,[r1,#0x00] - orr r2,r2,r3 - str r2,[r1,#0x00] - - /* Set bit 6 of the FPGA Power Control Register. If I could find some - * documentation on this, I could explain better why I am doing this, but - * for now, emperical evidence suggests that this disables the "shutdown" - * signal to the RS232 level shifter. - */ -/* - FPGA_PWR_CTRL_REG |= BIT_06; -*/ - ldr r1,=FPGA_BASE - ldrb r2,[r1,#0x05] - orr r2,r2,#0x20 -#ifdef ADD_COMPATIBILITY_FOR_THE_EVM_SOMEDAY - orr r2,r2,#0x40 -#endif - strb r2,[r1,#0x05] - - // Set up a stack [for calling C code] -#if defined(CYG_HAL_STARTUP_SLOADER) || defined(CYG_HAL_STARTUP_ROM) - // The startup stack is in internal SRAM - ldr sp,=__startup_stack - // This _MOST_DEFINATELY_ needs to be fixed - orr sp,sp,#0x10000000 -#else - // The startup stack is in SDRAM, at some virtual address, but - // we have not set up the MMU yet, so we need to initialize SP - // with the physical address of '__startup_stack' -#error "Somehow" -#endif - bl hal_mmu_init - - // Enable MMU - ldr r2,=10f - ldr r1,=MMU_Control_Init|MMU_Control_M - mcr MMU_CP,0,r1,MMU_Control,c0 - mov pc,r2 - - // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache - // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs -10: - nop - nop - nop - -#if 0 - ldr r3,=0x20000000 - str r1,[r3] - mrc MMU_CP,0,r1,MMU_Control,c0 - str r1,[r3, #0x04] - mrc p15,0,r1,c15,c1,0 - str r1,[r3, #0x08] - -here: - // b here -#endif -#else // PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT // This is all stolen from the ipaq setup // Make sure MMU is OFF mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading add r2,r0,#0x2000 // cache from the internal memory bank @@ -395,10 +202,25 @@ poll1: ldrh r1, [r0] ands r1, r1, #0x01 beq poll1 FAKE_LED_MACRO(5) +// -- stolen from proc-arm925.S (in Linux source) + mov r0, #0 +// There should be a CDL option to decide wheter we want the streaming +// option turned on or not (CONFIG_CPU_ARM925_NON_STREAMING_ON). Since +// Linux seems to work with the streaming mode disabled, we will disable +// it here. + orr r0,r0,#0x80 +#if defined(CONFIG_CPU_ARM925_TRANSPARENT_ON) +// We need to add CDL to decide whether or not to turn transparent +// mode on. For now, since it is disabled in Linux, we don't enable it +// here. + orr r0,r0,#0x2 +#endif + mcr p15, 0, r0, c15, c1, 0 @ write TI config register +// -- end of stuff stolen from proc-arm925.S (in Linux source) // Init Arm9 processor. // -------------------- mrs r0, cpsr // Get current mode bits. bic r0, r0, #0x1f // Clear mode bits. orr r0, r0, #0xd3 // Disable IRQs/FIQs, supervisor mode. @@ -570,10 +392,13 @@ again: nop nop nop FAKE_LED_MACRO(17) +#if 0 +// This should not be enabled here -- the variant hal enables it based on +// CDL. (Double check this at some point). // Enable I-Cache // ------------- mrc p15, 0x0, r1, c1, c0, 0x0 orr r1, r1, #0x1000 nop @@ -581,10 +406,11 @@ again: nop nop nop nop FAKE_LED_MACRO(18) +#endif // Initialize Traffic Controller (TC) // ---------------------------------- ldr r0, REG_TC_IMIF_PRIO mov r1, #0x0 @@ -673,29 +499,25 @@ again4: bne again4 FAKE_LED_MACRO(22) // ARM Clock Module Setup // ---------------------- - mov r1, #0x40 + mov r1, #0x40 // EN_APICK bit ldr r0, REG_ARM_IDLECT2 - strh r1, [r0] // CLKM, Clock domain control. + strh r1, [r0] // CLKM, Clock domain control. - mov r1, #0x01 // PER_EN bit + mov r1, #0x01 // PER_EN bit ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] // CLKM; Peripheral reset. + strh r1, [r0] // release peripheral reset. // Reset CLKM -#ifdef ORIGINAL_CODE - mov r1, #0x06 // Needed for UART[12] -#else - mov r1, #0x86 // Needed for UART[12] -#endif + mov r1, #0x86 // EN_TIMCK | EN_PERCK | EN_XCRPCK ldr r0, REG_ARM_IDLECT2 - strh r1, [r0] // CLKM, Clock domain control. + strh r1, [r0] // CLKM, Clock domain control. // Set CLKM to Sync-Scalable - mov r1, #0x1000 // Needed for UART[12] + mov r1, #0x1000 // CLOCK_SELECT = 010 ldr r0, REG_ARM_SYSST strh r1, [r0] // *revisit-skranz* is needed? mov r0, #0x1800 @@ -784,11 +606,10 @@ again9: str r1,[r3, #0x08] here: // b here #endif -#endif .endm #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT) #define PLATFORM_SETUP1 #endif @@ -948,17 +769,19 @@ VAL_TEST_DBG_CTRL_0: */ .word 0x00000007 VAL_MOD_CONF_CTRL_0: .word 0x0b000008 VAL_ARM_CKCTL: -#ifdef ORIGINAL_CODE - .word 0x110f -#else - .word 0x010f -#endif + .word 0x010f // TCDIV = 01, LCDDIV=11, PERDIV=11 VAL_DPLL1_CTL: +#if 0 .word 0x2710 +#else + .word 0x2CB0 // IOB=1, PLL_MULT=25, PLL_DIV=01(/2), PLL_ENABLE=1 + // It is remotely possible that this might set up + // the ARM to run at 150 MHz. +#endif VAL_TC_EMIFS_CS1_CONFIG_PRELIM: .word 0x00001149 VAL_TC_EMIFS_CS2_CONFIG_PRELIM: .word 0x00004158 VAL_TC_EMIFS_CS0_CONFIG: Index: packages/hal/arm/arm9/innovator/current/include/innovator.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/include/innovator.h,v retrieving revision 1.1 diff -u -5 -p -r1.1 innovator.h --- packages/hal/arm/arm9/innovator/current/include/innovator.h 5 Feb 2003 19:59:54 -0000 1.1 +++ packages/hal/arm/arm9/innovator/current/include/innovator.h 15 Apr 2003 19:19:50 -0000 @@ -53,439 +53,14 @@ //####DESCRIPTIONEND#### // //============================================================================= #include +#include // Platform specifics -// Memory mapping -#define FLASH_CS0_BASE 0x00000000 -#define FLASH_CS1_BASE 0x04000000 -#define FLASH_CS2_BASE 0x08000000 -#define FLASH_CS3_BASE 0x0C000000 -#define SDRAM_BASE 0x10000000 -#define INTERNAL_SRAM_BASE 0x20000000 - -// Most of this should be moved to a separate omap.h or omap_1510.h file -// CLKM Registers -#define CLKM_BASE 0xFFFECE00 -#define _CLKM_ARM_CKCTL 0x00 -#define _CLKM_ARM_IDLECT1 0x04 -#define _CLKM_ARM_IDLECT2 0x08 -#define _CLKM_ARM_EWUPCT 0x0C -#define _CLKM_ARM_RSTCT1 0x10 -#define _CLKM_ARM_RSTCT2 0x14 -#define _CLKM_ARM_SYSST 0x18 - -#define CLKM_ARM_CKCTL (volatile short *)(CLKM_BASE + _CLKM_ARM_CKCTL) -#define CLKM_ARM_IDLECT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT1) -#define CLKM_ARM_IDLECT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT2) -#define CLKM_ARM_EWUPCT (volatile short *)(CLKM_BASE + _CLKM_ARM_EWUPCT) -#define CLKM_ARM_RSTCT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT1) -#define CLKM_ARM_RSTCT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT2) -#define CLKM_ARM_SYSST (volatile short *)(CLKM_BASE + _CLKM_ARM_SYSST) - -// Watchdog Registers -#define WATCHDOG_BASE 0xFFFEC800 -#define _WD_CNTL_TIMER 0x00 -#define _WD_LOAD_TIM 0x04 -#define _WD_READ_TIM 0x04 -#define _WD_TIMER_MODE 0x08 - -#define WATCHDOG_CNTL_TIMER (volatile short *)(WATCHDOG_BASE + _WD_CNTL_TIMER) -#define WATCHDOG_LOAD_TIM (volatile short *)(WATCHDOG_BASE + _WD_LOAD_TIM) -#define WATCHDOG_READ_TIM (volatile short *)(WATCHDOG_BASE + _WD_READ_TIM) -#define WATCHDOG_TIMER_MODE (volatile short *)(WATCHDOG_BASE + _WD_TIMER_MODE) - -/* Nothing below this line has been scrubbed yet */ -/* DPLL Registers */ -#define DPLL1_BASE 0xFFFECF00 -#define DPLL2_BASE 0xFFFED000 -#define DPLL3_BASE 0xFFFED100 - -#define _DPLL_CTL_REG 0x00 - -#define DPLL1_CTL_REG (volatile short *)(DPLL1_BASE + _DPLL_CTL_REG) -#define DPLL2_CTL_REG (volatile short *)(DPLL2_BASE + _DPLL_CTL_REG) -#define DPLL3_CTL_REG (volatile short *)(DPLL3_BASE + _DPLL_CTL_REG) - -#define FPGA_BASE 0x08000000 /* CS2_BASE */ -#define CONFIG_BASE 0xFFFE1000 -#define TC_BASE 0xFFFECC00 - -/* FPGA Registers */ -#define FPGA_PWR_CTRL_REG (*(volatile char *)(FPGA_BASE + 0x05)) - -/* Configuration Registers */ -#define CONFIG_FUNC_MUX_CTRL_0 (*(volatile unsigned *)(CONFIG_BASE + 0x00)) -#define CONFIG_FUNC_MUX_CTRL_1 (*(volatile unsigned *)(CONFIG_BASE + 0x04)) -#define CONFIG_FUNC_MUX_CTRL_2 (*(volatile unsigned *)(CONFIG_BASE + 0x08)) - -/* Traffic Controller Registers */ -#define TC_IMIF_PRIO (*(volatile unsigned *)(TC_BASE + 0x00)) -#define TC_EMIFS_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x04)) -#define TC_EMIFF_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x08)) -#define TC_EMIFS_CONFIG_REG (*(volatile unsigned *)(TC_BASE + 0x0C)) -#define TC_EMIFS_CS0_CONFIG (*(volatile unsigned *)(TC_BASE + 0x10)) -#define TC_EMIFS_CS1_CONFIG (*(volatile unsigned *)(TC_BASE + 0x14)) -#define TC_EMIFS_CS2_CONFIG (*(volatile unsigned *)(TC_BASE + 0x18)) -#define TC_EMIFS_CS3_CONFIG (*(volatile unsigned *)(TC_BASE + 0x1C)) -#define TC_EMIFF_SDRAM_CONFIG (*(volatile unsigned *)(TC_BASE + 0x20)) -#define TC_EMIFF_MRS (*(volatile unsigned *)(TC_BASE + 0x24)) -#define TC_TIMEOUT1 (*(volatile unsigned *)(TC_BASE + 0x28)) -#define TC_TIMEOUT2 (*(volatile unsigned *)(TC_BASE + 0x2C)) -#define TC_TIMEOUT3 (*(volatile unsigned *)(TC_BASE + 0x30)) -#define TC_ENDIANISM (*(volatile unsigned *)(TC_BASE + 0x34)) - -/* Believe it or not, these actually make the code more readable in a few - * places. - */ -#ifndef BIT_00 -#define BIT_00 0x00000001 -#define BIT_01 0x00000002 -#define BIT_02 0x00000004 -#define BIT_03 0x00000008 -#define BIT_04 0x00000010 -#define BIT_05 0x00000020 -#define BIT_06 0x00000040 -#define BIT_07 0x00000080 -#define BIT_08 0x00000100 -#define BIT_09 0x00000200 -#define BIT_10 0x00000400 -#define BIT_11 0x00000800 -#define BIT_12 0x00001000 -#define BIT_13 0x00002000 -#define BIT_14 0x00004000 -#define BIT_15 0x00008000 -#define BIT_16 0x00010000 -#define BIT_17 0x00020000 -#define BIT_18 0x00040000 -#define BIT_19 0x00080000 -#define BIT_20 0x00100000 -#define BIT_21 0x00200000 -#define BIT_22 0x00400000 -#define BIT_23 0x00800000 -#define BIT_24 0x01000000 -#define BIT_25 0x02000000 -#define BIT_26 0x04000000 -#define BIT_27 0x08000000 -#define BIT_28 0x10000000 -#define BIT_29 0x20000000 -#define BIT_30 0x40000000 -#define BIT_31 0x80000000 -#endif - -// We are using this -#define INNOVATOR_FLASH_VIRT_BASE 0x10000000 -// #define INNOVATOR_FLASH_PHYS_BASE 0x00000000 +// We are using this -- we should change INNOVATOR to OMAP #define INNOVATOR_SDRAM_PHYS_BASE 0x10000000 +#define INNOVATOR_FLASH_VIRT_BASE 0x10000000 -#if 0 -#define INNOVATOR_BASE INNOVATOR_REGS_PHYS_BASE - -//----------------------------------------------------------------------------- -// Boot control -// Note: this register is actually write-bit-to-clear-it -#define INNOVATOR_BOOT_CR (INNOVATOR_BASE + 0x0000) - -#define INNOVATOR_BOOT_CR_BM 0x00000001 -#define INNOVATOR_BOOT_CR_HM 0x00000002 -#define INNOVATOR_BOOT_CR_RE 0x00000004 - -//----------------------------------------------------------------------------- -// DPSRAM config -#define INNOVATOR_DPSRAM_BASE (INNOVATOR_BASE + 0x0030) -#define _DPSRAM0_SR 0x0000 -#define _DPSRAM0_LCR 0x0004 -#define _DPSRAM1_SR 0x0008 -#define _DPSRAM1_LCR 0x000c - -#define _DPSRAM0_LCR_INIT 0x00000000 -#define _DPSRAM1_LCR_INIT 0x00000000 - -//----------------------------------------------------------------------------- -// IO controller -#define INNOVATOR_IOCR_BASE (INNOVATOR_BASE + 0x0040) -#define _IOCR_SDRAM 0x0000 -#define _IOCR_EBI 0x0004 -#define _IOCR_UART 0x0008 -#define _IOCR_TRACE 0x000c - -#define _IOCR_OC_PCI 0x00000008 -#define _IOCR_OC_FAST 0x00000004 -#define _IOCR_OC_SLOW 0x00000000 -#define _IOCR_IO_STRIPE 0x00000002 -#define _IOCR_LOCK 0x00000001 - -#define INNOVATOR_IOCR_SDRAM_INIT (_IOCR_OC_FAST | _IOCR_IO_STRIPE | _IOCR_LOCK) -#define INNOVATOR_IOCR_EBI_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK) -#define INNOVATOR_IOCR_UART_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK) - - -//----------------------------------------------------------------------------- -// Memory mapping -#define INNOVATOR_MMAP_BASE (INNOVATOR_BASE + 0x0080) -#define _MMAP_REGISTERS 0x0000 -#define _MMAP_SRAM0 0x0010 -#define _MMAP_SRAM1 0x0014 -#define _MMAP_DPSRAM0 0x0020 -#define _MMAP_DPSRAM1 0x0024 -#define _MMAP_SDRAM0 0x0030 -#define _MMAP_SDRAM1 0x0034 -#define _MMAP_EBI0 0x0040 -#define _MMAP_EBI1 0x0044 -#define _MMAP_EBI2 0x0048 -#define _MMAP_EBI3 0x004c -#define _MMAP_PLD0 0x0050 -#define _MMAP_PLD1 0x0054 -#define _MMAP_PLD2 0x0058 -#define _MMAP_PLD3 0x005c - -#define _MMAP_SIZE_16K (13<<7) -#define _MMAP_SIZE_64K (15<<7) -#define _MMAP_SIZE_128K (16<<7) -#define _MMAP_SIZE_1M (19<<7) -#define _MMAP_SIZE_4M (21<<7) -#define _MMAP_SIZE_16M (23<<7) -#define _MMAP_SIZE_32M (24<<7) -#define _MMAP_SIZE_64M (25<<7) - -#define _MMAP_PREFETCH 0x00000000 -#define _MMAP_NOPREFETCH 0x00000002 - -#define _MMAP_ENABLE 0x00000001 -#define _MMAP_DISABLE 0x00000000 - -#define _MMAP_REGISTERS_INIT (INNOVATOR_REGS_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) -#define _MMAP_SRAM0_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_SRAM1_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00020000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_DPSRAM0_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00040000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_DPSRAM1_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00050000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_SDRAM0_INIT (INNOVATOR_SDRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_SDRAM1_INIT (INNOVATOR_SDRAM_PHYS_BASE + 0x04000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_EBI0_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00000000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_EBI1_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00400000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_EBI2_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00800000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_EBI3_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00c00000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) -#define _MMAP_PLD0_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) -//#define _MMAP_PLD1_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00004000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) -#define _MMAP_PLD1_INIT (0x0f000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) -#define _MMAP_PLD2_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00008000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) -#define _MMAP_PLD3_INIT (INNOVATOR_PLD_PHYS_BASE + 0x0000c000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) - - - - - -//----------------------------------------------------------------------------- -// Timers -#define INNOVATOR_TIMER0_CR (INNOVATOR_BASE+0x0200) -#define INNOVATOR_TIMER0_PRE (INNOVATOR_BASE+0x0210) -#define INNOVATOR_TIMER0_LIMIT (INNOVATOR_BASE+0x0220) -#define INNOVATOR_TIMER0_READ (INNOVATOR_BASE+0x0230) - -#define INNOVATOR_TIMER1_CR (INNOVATOR_BASE+0x0240) -#define INNOVATOR_TIMER1_PRE (INNOVATOR_BASE+0x0250) -#define INNOVATOR_TIMER1_LIMIT (INNOVATOR_BASE+0x0260) -#define INNOVATOR_TIMER1_READ (INNOVATOR_BASE+0x0270) - -#define INNOVATOR_TIMER_CR_MODE_HEARBEAT 0x00000000 -#define INNOVATOR_TIMER_CR_MODE_ONE_SHOT 0x00000001 -#define INNOVATOR_TIMER_CR_IE 0x00000004 -#define INNOVATOR_TIMER_CR_CI 0x00000008 -#define INNOVATOR_TIMER_CR_S 0x00000010 - -//----------------------------------------------------------------------------- -// Serial -#define INNOVATOR_UART0_BASE (INNOVATOR_BASE+0x0280) -#define _UART_RSR 0x0000 -#define _UART_RDS 0x0004 -#define _UART_RD 0x0008 -#define _UART_TSR 0x000c -#define _UART_TD 0x0010 -#define _UART_FCR 0x0014 -#define _UART_IES 0x0018 -#define _UART_IEC 0x001c -#define _UART_ISR 0x0020 -#define _UART_IID 0x0024 -#define _UART_MC 0x0028 -#define _UART_MCR 0x002c -#define _UART_MSR 0x0030 -#define _UART_DIV_LO 0x0034 -#define _UART_DIV_HI 0x0038 - -#define _UART_RSR_RX_LEVEL 0x0000001f - -#define _UART_TSR_TXI 0x00000080 - -#define _UART_FCR_TC 0x00000001 -#define _UART_FCR_RC 0x00000002 -#define _UART_FCR_TX_THR_15 0x0000001c -#define _UART_FCR_RX_THR_1 0x00000000 - -#define _UART_INTS_RE 0x00000001 -#define _UART_INTS_RI _UART_INTS_RE -#define _UART_INTS_TE 0x00000002 -#define _UART_INTS_TI _UART_INTS_TE -#define _UART_INTS_TIE 0x00000004 -#define _UART_INTS_TII _UART_INTS_TIE -#define _UART_INTS_ME 0x00000008 -#define _UART_INTS_MI _UART_INTS_ME - - -#define _UART_MC_8BIT 0x00000003 -#define _UART_MC_1STOP 0x00000000 -#define _UART_MC_PARITY_NONE 0x00000000 - -//----------------------------------------------------------------------------- -// Clock controller -#define INNOVATOR_CLK_BASE (INNOVATOR_BASE + 0x0300) -#define _CLK_PLL1_NCNT 0x0000 -#define _CLK_PLL1_MCNT 0x0004 -#define _CLK_PLL1_KCNT 0x0008 -#define _CLK_PLL1_CTRL 0x000c -#define _CLK_PLL2_NCNT 0x0010 -#define _CLK_PLL2_MCNT 0x0014 -#define _CLK_PLL2_KCNT 0x0018 -#define _CLK_PLL2_CTRL 0x001c -#define _CLK_DERIVE 0x0020 -#define _CLK_STATUS 0x0024 -#define _CLK_AHB1_COUNT 0x0028 - -#define _CLK_PLL1_CTRL_P 0x00000001 -#define _CLK_PLL2_CTRL_P 0x00000001 - -#define _CLK_DERIVE_BP1 (1<<12) -#define _CLK_DERIVE_BP2 (1<<13) - -#define _CLK_STATUS_L1 0x00000001 -#define _CLK_STATUS_L2 0x00000002 -#define _CLK_STATUS_C1 0x00000004 -#define _CLK_STATUS_C2 0x00000008 - -// Settings from Altera example code. Note that this differs from the -// magic values described in the manual. I think the values are -// supposed to disable the PLLs, making the core run at 25MHz and -// peripherals at 12.5MHz -#define _CLK_PLL1_CTRL_INIT 0x00001064 -#define _CLK_PLL2_CTRL_INIT 0x00001064 -#define _CLK_DERIVE_INIT 0x00003010 - -//----------------------------------------------------------------------------- -// Expansion Bus Interface -#define INNOVATOR_EBI_CR (INNOVATOR_BASE + 0x0380) - -#define INNOVATOR_EBI_CR_EO 0x00000008 - -#define INNOVATOR_EBI_CR_INIT (INNOVATOR_EBI_CR_EO) - -//----------------------------------------------------------------------------- -// SDRAM controller -#define INNOVATOR_SDRAM_BASE (INNOVATOR_BASE + 0x0400) -#define _SDRAM_TIMING1 0x0000 -#define _SDRAM_TIMING2 0x0004 -#define _SDRAM_CONFIG 0x0008 -#define _SDRAM_REFRESH 0x000c -#define _SDRAM_ADDR 0x0010 -#define _SDRAM_INIT 0x001c -#define _SDRAM_MODE0 0x0020 -#define _SDRAM_MODE1 0x0024 -#define INNOVATOR_SDRAM_WIDTH (INNOVATOR_BASE + 0x007c) - - -#define _SDRAM_WIDTH_W 0x00000002 -#define _SDRAM_WIDTH_LK 0x00000001 - -#if 0 -// Max delays -#define _SDRAM_TIMING1_INIT 0x00009124 -// CAS-2, 8 words burst, 3 clock refresh -#define _SDRAM_TIMING2_INIT 0x00000788 -// SDR -#define _SDRAM_CONFIG_INIT 0x00000000 -// Refresh period of 15us - at a clock of 75MHz that's 1125 cycles -#define _SDRAM_REFRESH_INIT 1125 -// Rows (12) & columns (10) -#define _SDRAM_ADDR_INIT 0x0000ca80 -// SDRAM mode (from Micron MT48LC16M8A2 manual) -// M0-2: burst length = 3 (8 words) -// M3 : burst type = 0 (sequential vs interleaved) -// M4-6: CAS latency = 2 -// M7-8: operating mode = 0 -// M9 : write burst mode = 0 (writes are also in burst) -#define _SDRAM_MODE0_INIT ((2<<4)|3) -// Unused (for DDR) -#define _SDRAM_MODE1_INIT 0x00000000 -#endif - -#define _SDRAM_INIT_EN 0x00008000 -#define _SDRAM_INIT_PR 0x00004000 -#define _SDRAM_INIT_LM 0x00002000 -#define _SDRAM_INIT_LEM 0x00001000 -#define _SDRAM_INIT_RF 0x00000800 -#define _SDRAM_INIT_BS 0x00000400 -#define _SDRAM_INIT_SR 0x00000200 - -//----------------------------------------------------------------------------- -// Watchdog controller -#define INNOVATOR_WDOG_CR (INNOVATOR_BASE+0x0a00) -#define INNOVATOR_WDOG_COUNT (INNOVATOR_BASE+0x0a04) -#define INNOVATOR_WDOG_RELOAD (INNOVATOR_BASE+0x0a08) - -//----------------------------------------------------------------------------- -// Interrupt controller -#define INNOVATOR_INT_MASK_SET (INNOVATOR_BASE+0x0c00) -#define INNOVATOR_INT_MASK_CLEAR (INNOVATOR_BASE+0x0c04) -#define INNOVATOR_INT_SOURCE_STATUS (INNOVATOR_BASE+0x0c08) -#define INNOVATOR_INT_REQUEST_STATUS (INNOVATOR_BASE+0x0c0c) -#define INNOVATOR_INT_ID (INNOVATOR_BASE+0x0c10) -#define INNOVATOR_INT_PLD_PRIORITY (INNOVATOR_BASE+0x0c14) -#define INNOVATOR_INT_INT_MODE (INNOVATOR_BASE+0x0c18) -#define INNOVATOR_INT_PRIORITY_0 (INNOVATOR_BASE+0x0c80) -#define INNOVATOR_INT_PRIORITY_1 (INNOVATOR_BASE+0x0c84) -#define INNOVATOR_INT_PRIORITY_2 (INNOVATOR_BASE+0x0c88) -#define INNOVATOR_INT_PRIORITY_3 (INNOVATOR_BASE+0x0c8c) -#define INNOVATOR_INT_PRIORITY_4 (INNOVATOR_BASE+0x0c90) -#define INNOVATOR_INT_PRIORITY_5 (INNOVATOR_BASE+0x0c94) -#define INNOVATOR_INT_PRIORITY_6 (INNOVATOR_BASE+0x0c98) -#define INNOVATOR_INT_PRIORITY_7 (INNOVATOR_BASE+0x0c9c) -#define INNOVATOR_INT_PRIORITY_8 (INNOVATOR_BASE+0x0ca0) -#define INNOVATOR_INT_PRIORITY_9 (INNOVATOR_BASE+0x0ca4) -#define INNOVATOR_INT_PRIORITY_10 (INNOVATOR_BASE+0x0ca8) -#define INNOVATOR_INT_PRIORITY_11 (INNOVATOR_BASE+0x0cac) -#define INNOVATOR_INT_PRIORITY_12 (INNOVATOR_BASE+0x0cb0) -#define INNOVATOR_INT_PRIORITY_13 (INNOVATOR_BASE+0x0cb4) -#define INNOVATOR_INT_PRIORITY_14 (INNOVATOR_BASE+0x0cb8) -#define INNOVATOR_INT_PRIORITY_15 (INNOVATOR_BASE+0x0cbc) -#define INNOVATOR_INT_PRIORITY_16 (INNOVATOR_BASE+0x0cc0) - -#define INNOVATOR_INT_SOURCE_P0 0x00000001 -#define INNOVATOR_INT_SOURCE_P1 0x00000002 -#define INNOVATOR_INT_SOURCE_P2 0x00000004 -#define INNOVATOR_INT_SOURCE_P3 0x00000008 -#define INNOVATOR_INT_SOURCE_P4 0x00000010 -#define INNOVATOR_INT_SOURCE_P5 0x00000020 -#define INNOVATOR_INT_SOURCE_IP 0x00000040 -#define INNOVATOR_INT_SOURCE_UA 0x00000080 -#define INNOVATOR_INT_SOURCE_T0 0x00000100 -#define INNOVATOR_INT_SOURCE_T1 0x00000200 -#define INNOVATOR_INT_SOURCE_PS 0x00000400 -#define INNOVATOR_INT_SOURCE_EE 0x00000800 -#define INNOVATOR_INT_SOURCE_PE 0x00001000 -#define INNOVATOR_INT_SOURCE_AE 0x00002000 -#define INNOVATOR_INT_SOURCE_CT 0x00004000 -#define INNOVATOR_INT_SOURCE_CR 0x00008000 -#define INNOVATOR_INT_SOURCE_FC 0x00010000 - -#define INNOVATOR_INT_PRIORITY_FIQ 0x00000040 -#define INNOVATOR_INT_PRIORITY_LVL_mask 0x0000003f - -//----------------------------------------------------------------------------- -// PLD -#define INNOVATOR_PLD_BASE INNOVATOR_PLD_PHYS_BASE - -#define INNOVATOR_PLD_LEDS (INNOVATOR_PLD_BASE + 0x0100) - - -#endif #endif // CYGONCE_INNOVATOR_H //----------------------------------------------------------------------------- // end of innovator.h Index: packages/hal/arm/arm9/innovator/current/misc/redboot_SRAM.ecm =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/misc/redboot_SRAM.ecm,v retrieving revision 1.2 diff -u -5 -p -r1.2 redboot_SRAM.ecm --- packages/hal/arm/arm9/innovator/current/misc/redboot_SRAM.ecm 13 Feb 2003 01:01:09 -0000 1.2 +++ packages/hal/arm/arm9/innovator/current/misc/redboot_SRAM.ecm 15 Apr 2003 19:19:50 -0000 @@ -45,18 +45,10 @@ cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_ cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { inferred_value 0 }; -cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { - user_value 0 -}; - -cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { - user_value 0 -}; - cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { inferred_value 1 }; cdl_option CYGSEM_HAL_ROM_MONITOR { @@ -79,10 +71,14 @@ cdl_option CYGPRI_HAL_ROM_MLT { user_value SRAM }; cdl_component CYGBLD_BUILD_REDBOOT { user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00030000 }; cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { inferred_value 0x10008000 }; Index: packages/hal/arm/arm9/innovator/current/src/innovator_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/src/innovator_misc.c,v retrieving revision 1.2 diff -u -5 -p -r1.2 innovator_misc.c --- packages/hal/arm/arm9/innovator/current/src/innovator_misc.c 13 Feb 2003 01:01:09 -0000 1.2 +++ packages/hal/arm/arm9/innovator/current/src/innovator_misc.c 15 Apr 2003 19:19:50 -0000 @@ -213,20 +213,20 @@ hal_mmu_init(void) // Platform specific initialization void plf_hardware_init(void) { -#ifdef LATER - // Disable PLD interrupts - HAL_WRITE_UINT32(INNOVATOR_INT_MASK_CLEAR, - INNOVATOR_INT_SOURCE_P0 | INNOVATOR_INT_SOURCE_P1 | - INNOVATOR_INT_SOURCE_P2 | INNOVATOR_INT_SOURCE_P3 | - INNOVATOR_INT_SOURCE_P4 | INNOVATOR_INT_SOURCE_P5); - // Make PLD0 generate IRQ - HAL_WRITE_UINT32(INNOVATOR_INT_PRIORITY_0, 0); -#endif cyg_uint8 tmp; + + // Disable all interrupt sources -- we enable IRQ01 of interrupt + // handler 1 so that it passes in the interrupts from interrupt + // handler 2. We also ensure that IRQ01 of IH1 is configured + // to be edge triggered, routed to IRQ, and priority 0. + HAL_WRITE_UINT32(IH1_MIR, 0xFFFFFFFD); + HAL_WRITE_UINT32(IH2_MIR, 0xFFFFFFFF); + HAL_WRITE_UINT32(IH1_ILR01, 2); + // This should be protected by some sort of #ifdef to test to see if // the ethernet has been enabled or not. I'll add that later. HAL_READ_UINT8(0x0800000B, tmp); HAL_WRITE_UINT8(0x0800000B, tmp & ~1); HAL_DELAY_US(750); @@ -249,10 +249,24 @@ hal_clock_initialize(cyg_uint32 period) // Unmask timer 0 interrupt HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 ); HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC ); #endif + cyg_uint32 cntl_timer; + // Enable the clock and halt the timer + cntl_timer = (CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE_LOG - 1) << 2 | 0x22; + HAL_WRITE_UINT32(TIMER1_CNTL_TIMER, cntl_timer); + + // Load the timer + HAL_WRITE_UINT32(TIMER1_LOAD_TIM, period); + + // Start the timer + HAL_WRITE_UINT32(TIMER1_CNTL_TIMER, cntl_timer | 1); + + // Unmask timer 0 interrupt + HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 0, 1 ); + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC ); } // This routine is called during a clock interrupt. void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) @@ -286,156 +300,217 @@ hal_clock_read(cyg_uint32 *pvalue) // Delay for some number of micro-seconds // void hal_delay_us(cyg_int32 usecs) { -#ifdef LATER - // Use timer 2 - cyg_uint32 cr; - // Divide by 1000000 in two steps to preserve precision. - cyg_uint32 wait_clocks = ((CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/100000)*usecs)/10; - - HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, 0); - HAL_WRITE_UINT32(INNOVATOR_TIMER1_PRE, 0); - HAL_WRITE_UINT32(INNOVATOR_TIMER1_LIMIT, wait_clocks); - cr = INNOVATOR_TIMER_CR_MODE_ONE_SHOT|INNOVATOR_TIMER_CR_CI; - HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, cr); - HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, cr | INNOVATOR_TIMER_CR_S); - - // wait for start bit to clear - do { - HAL_READ_UINT32(INNOVATOR_TIMER1_CR, cr); - } while ((INNOVATOR_TIMER_CR_S & cr) != 0); - - //clear interrupt flag - HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, 0); -#else -#if 0 - volatile unsigned long long x; - volatile unsigned long long loop_count = usecs / 10 + 1; - - for (x = 0; x < loop_count; x++) ; -#else - volatile cyg_uint32 *CNTL_TIMER = (volatile cyg_uint32 *)(0xFFFEC500 + 0x00); - volatile cyg_uint32 *LOAD_TIM = (volatile cyg_uint32 *)(0xFFFEC500 + 0x04); - volatile cyg_uint32 *READ_TIM = (volatile cyg_uint32 *)(0xFFFEC500 + 0x08); cyg_uint32 timer_val, prev_val; int too_long = 0; if (usecs <= 0) { return; } else if (usecs > 357913941) { /* Clamp at MAX_INT32 / 6 */ usecs = 357913941; } - /* Enable the clock and halt the timer */ - HAL_WRITE_UINT32(CNTL_TIMER, 0x00000020); - - /* Load the timer */ - HAL_WRITE_UINT32(LOAD_TIM, 6 * usecs); + // Enable the clock and halt the timer + HAL_WRITE_UINT32(TIMER2_CNTL_TIMER, 0x00000020); - /* Start the timer */ - HAL_READ_UINT32(READ_TIM, prev_val); - HAL_WRITE_UINT32(CNTL_TIMER, 0x00000021); + // Load the timer + HAL_WRITE_UINT32(TIMER2_LOAD_TIM, 6 * usecs); - /* Wait for it to load (but not too long) */ + // Start the timer + HAL_READ_UINT32(TIMER2_READ_TIM, prev_val); + HAL_WRITE_UINT32(TIMER2_CNTL_TIMER, 0x00000021); + + // Wait for it to load (but not too long). We do this so that, when + // we execute the next loop, 'timer_val' will (hopefully) have a + // non-zero value. We were having a problem in that the ARM (which was + // running at 168MHz) was blowing through this code so fast that the + // timer (which is running at 6MHz) did not have time to load the + // new non-zero countdown value before we tried to read it back. do { - HAL_READ_UINT32(READ_TIM, timer_val); + HAL_READ_UINT32(TIMER2_READ_TIM, timer_val); if (++too_long >= 100) { break; } } while (timer_val == prev_val); /* Wait for it to count down to zero */ do { - HAL_READ_UINT32(READ_TIM, timer_val); + HAL_READ_UINT32(TIMER2_READ_TIM, timer_val); } while (timer_val > 0); -#endif -#endif } // ------------------------------------------------------------------------- // This routine is called to respond to a hardware interrupt (IRQ). It // should interrogate the hardware and return the IRQ vector number. int hal_IRQ_handler(void) { -#ifdef LATER - int vec; - cyg_uint32 isr; + int irq_code; + int offset = 0; - HAL_READ_UINT32(INNOVATOR_INT_REQUEST_STATUS, isr); - for (vec = CYGNUM_HAL_INTERRUPT_PLD_0; - vec <= CYGNUM_HAL_INTERRUPT_FAST_COMMS; vec++) { - if (isr & (1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); - HAL_WRITE_UINT32(INNOVATOR_INT_MASK_CLEAR, 1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); - HAL_WRITE_UINT32(INNOVATOR_INT_MASK_SET, 1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); -#endif + if (vector < CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK) { + itr = IH1_ITR; + control_reg = IH1_CONTROL_REG; + } else { + itr = IH2_ITR; + control_reg = IH2_CONTROL_REG; + vector -= CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK; + clear_ih1 = true; + } + // Clear the ITR register + + // WARNING WARNING WARNING DANGER WILL ROBINSON WARNING WARNING WARNING + // This will clear a pending edge triggered interrupt that occured + // since the time that we received the previous edge triggered + // interrupt. (On the OMAP, simply determining that we received an + // edge triggered interrupt clears the fact that we received an edge + // triggered interrrupt -- if we receive another one, it will be recorded + // in the ITR and this will clear that). This feels like a dangerous + // thing to do here, but as long as all edge triggered interrupt + // handlers first acknowledge the receipt of the interrupt, and then + // determine the cause and/or the number of things to do, it should be + // ok. + HAL_READ_UINT32(itr, reg); + HAL_WRITE_UINT32(itr, reg & ~(1 << vector)); + + // Clear the IRQ output + HAL_WRITE_UINT32(control_reg, 1); + + // Later, rinse, repeat for interrupt handler 1 if this was an interrupt + // from IH2 + if (clear_ih1) { + HAL_READ_UINT32(IH1_ITR, reg); + HAL_WRITE_UINT32(IH1_ITR, reg & ~(1 << 1)); + HAL_WRITE_UINT32(IH1_CONTROL_REG, 1); + } } void hal_interrupt_configure(int vector, int level, int up) { -#ifdef LATER + cyg_uint32 *ilr; + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); - CYG_ASSERT(level || up, "Cannot do falling edge"); -#endif + + // The OMAP only supports rising edge and high level interrupts + CYG_ASSERT(up, "Cannot do falling edge or active low interrupts"); + + CYG_ASSERT(level == true || level == false, "Illegal value for level"); + + if (vector < CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK) { + ilr = (cyg_uint32 *)(IH1_BASE + 4 * vector); + } else { + ilr = (cyg_uint32 *)(IH2_BASE + 4 * (vector - + CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK)); + } + + // we configure all interrupts as IRQ's (as opposed to FIQ's) with a + // priority of 0, by default + HAL_WRITE_UINT32(ilr, level << 1); } void hal_interrupt_set_level(int vector, int level) { -#ifdef LATER - cyg_uint32 reg; + cyg_uint32 *ilr; + cyg_uint32 reg; CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); - CYG_ASSERT(level <= 63 && level >= 0, "Invalid level"); - HAL_READ_UINT32(INNOVATOR_INT_PRIORITY_0+4*vector, reg); - reg &= ~INNOVATOR_INT_PRIORITY_LVL_mask; - reg |= (level & INNOVATOR_INT_PRIORITY_LVL_mask); - HAL_WRITE_UINT32(INNOVATOR_INT_PRIORITY_0+4*vector, reg); -#endif + CYG_ASSERT(level >= 0 && level <= 31, "Invalid level"); + + if (vector < CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK) { + ilr = (cyg_uint32 *)(IH1_BASE + 4 * vector); + } else { + ilr = (cyg_uint32 *)(IH2_BASE + 4 * (vector - + CYGNUM_HAL_INTERRUPT_IH1_IH2_BREAK)); + } + + HAL_READ_UINT32(ilr, reg); + reg &= ~IH_INT_PRIORITY_LVL_mask; + reg |= level << 2; + HAL_WRITE_UINT32(ilr, reg); } #include CYGHWR_MEMORY_LAYOUT_H typedef void code_fun(void); void innovator_program_new_stack(void *func) Index: packages/hal/arm/arm9/innovator/current/src/redboot_cmds.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/innovator/current/src/redboot_cmds.c,v retrieving revision 1.1 diff -u -5 -p -r1.1 redboot_cmds.c --- packages/hal/arm/arm9/innovator/current/src/redboot_cmds.c 5 Feb 2003 19:59:54 -0000 1.1 +++ packages/hal/arm/arm9/innovator/current/src/redboot_cmds.c 15 Apr 2003 19:19:50 -0000 @@ -1,11 +1,10 @@ -#if 0 //========================================================================== // // redboot_cmds.c // -// OMAP1510DC EVM [platform] specific RedBoot commands +// OMAP Innovator [platform] specific RedBoot commands // //========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. @@ -47,11 +46,11 @@ // Purpose: // Description: // // This code is part of RedBoot (tm). It was modified from "redboot_cmds" // for the iPaq by wpd in order to add some platform specific commands to -// the OMAP1510DC EVM platform. +// the innovator platform. // //####DESCRIPTIONEND#### // //========================================================================== @@ -61,10 +60,98 @@ #include #include #include #include +static void do_init_dsp(int argc, char *argv[]); + +RedBoot_cmd("init_dsp", + "Initialize the DSP and place it in an idle loop.", + "", + do_init_dsp + ); + +/************************************************************************ + * The following array was created by compiling the following snippet + * of assembly code and generating a listing file: + * + * + * _watchdog_disable: + * MOV #13316, AR3 ; |6| + * MOV #245, port(*AR3) ; |6| + * MOV #160, port(*AR3) ; |7| + * loop: IDLE + * B loop + * + * This was assembled using the following command: + * + * prompt$ masm55 -L ioport.asm + * + * (using the Linux based version of the tool chain) to produce the following + * + * listing file: + * + * 47 000000 _watchdog_disable: + * 48 000000 7634 MOV #13316, AR3 ; |6| + * 000002 04B8 + * 49 000004 FB61 MOV #245, port(*AR3) ; |6| + * 000006 00F5 + * 000008 9A + * 50 000009 FB61 MOV #160, port(*AR3) ; |7| + * 00000b 00A0 + * 00000d 9A + * 51 00000e 7A00 loop: IDLE + * 000010 000C + * 52 000012 4A7A B loop + * + * Finally, the instruction stream was extracted into the following array: + */ +static char idle_loop[] = { + 0x76, 0x34, /* MOV #0x3404, AR3 */ + 0x04, 0xB8, + 0xFB, 0x61, /* MOV #0xF5, port(*AR3) */ + 0x00, 0xF5, + 0x9A, + 0xFB, 0x61, /* MOV #0xA0, port(*AR3) */ + 0x00, 0xA0, + 0x9A, + 0x7A, 0x00, /* loop: IDLE */ + 0x00, 0x0C, + 0x4A, 0x7A, /* B loop */ +}; + +static void +do_init_dsp(int argc, + char *argv[]) +{ + /* Bit bang this first, then we'll do it right later */ + /* Place the DSP in reset -- clear the DEP_EN bit of ARM_RSTCT1 */ + *CLKM_ARM_RSTCT1 &= ~(BIT_01 | BIT_02); + + /* Now enable the EMIF configuration registers and MPUI control logic */ + *CLKM_ARM_RSTCT1 |= BIT_02; + + /* Set the DSP boot mode to "branch to 0x10000" mode */ + *MPUI_DSP_BOOT_CONFIG = 5; + + /* Set the EN_APICK bit of ARM_IDCT2 to enable the MPUI clock */ + *CLKM_ARM_IDLECT2 |= BIT_06; + + /* Copy the idle loop insruction stream to address 0x10000 in the DSP */ + memcpy((void *)MPUI_PORT_RAM + 0x10000, idle_loop, sizeof(idle_loop)); + + /* Now set the DSP_EN bit in ARM_RSTCT1 to 1 to release the DSP from reset */ + *CLKM_ARM_RSTCT1 |= BIT_01; + + diag_printf("DSP Initialized\n"); +} + +#if 0 +/************************************************************************ + * The following commands are for testing only. They are sometimes + * enabled and sometimes disabled, depending on my mood of the day. + ************************************************************************/ static void do_mem(int argc, char *argv[]); static void do_try_reset(int argc, char *argv[]); static void do_testsdram(int argc, char *argv[]); static void do_delay(int argc, char *argv[]); @@ -92,10 +179,17 @@ RedBoot_cmd("delay", "[-c count] amount", do_delay ); +RedBoot_cmd("hack", + "Perform whatever hack wpd feels like testing today", + "(none)", + do_hack + ); + + static void do_mem(int argc, char *argv[]) { struct option_info opts[4]; @@ -294,8 +388,20 @@ do_delay(int argc, for (i = 0; i < count; i++) { diag_printf("Delaying %d useconds...", value); HAL_DELAY_US(value); diag_printf("Done\n"); } +} + +static void +do_hack(int argc, + char *argv[]) +{ + register unsigned i; + + diag_printf("starting..."); + for (i = 0x00000000; i < 0x80000000; i++) asm volatile ("nop;"); + diag_printf("done\n"); + } #endif Index: packages/hal/arm/arm9/var/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/ChangeLog,v retrieving revision 1.7 diff -u -5 -p -r1.7 ChangeLog --- packages/hal/arm/arm9/var/current/ChangeLog 8 Jan 2003 19:47:34 -0000 1.7 +++ packages/hal/arm/arm9/var/current/ChangeLog 15 Apr 2003 19:19:50 -0000 @@ -1,5 +1,12 @@ +2003-04-15 Patrick Doyle + + * include/hal_cache.h: Added + 'CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE' (stolen from the Linux code + for the innovator) because the 'CYGHWR_HAL_ARM_ARM9_CLEAN_CACHE' + feature did not work correctly on the innovator. + 2003-01-08 Patrick Doyle * include/hal_cache.h: Changed HAL_ICACHE_LINE_SIZE and HAL_DCACHE_LINE_SIZE to match the documentation from TI. Now the kcache2 test passes the two tests that it runs. Index: packages/hal/arm/arm9/var/current/include/hal_cache.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/include/hal_cache.h,v retrieving revision 1.7 diff -u -5 -p -r1.7 hal_cache.h --- packages/hal/arm/arm9/var/current/include/hal_cache.h 8 Jan 2003 19:47:37 -0000 1.7 +++ packages/hal/arm/arm9/var/current/include/hal_cache.h 15 Apr 2003 19:19:51 -0000 @@ -111,11 +111,12 @@ # define HAL_DCACHE_WAYS 2 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) # define HAL_WRITE_BUFFER 64 -# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache +// #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache +# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE // use code stolen from Linux #elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T) # define HAL_ICACHE_SIZE 0x1000 # define HAL_ICACHE_LINE_SIZE 16 # define HAL_ICACHE_WAYS 4 @@ -364,10 +365,31 @@ CYG_MACRO_START "bne 1b;" \ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \ : "=r" (_tmp1), "=r" (_tmp2) \ : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \ "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \ + : "r0" /* Clobber list */ \ + ); \ +CYG_MACRO_END +#elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE) +/* + * 'Clean & Invalidate whole DCache' + * NOTE: Requires TI925T Configuration Register C bit <- 0 + * for clean and invalidate of both D-Cache sets. + */ +#define HAL_DCACHE_SYNC() \ +CYG_MACRO_START \ + asm volatile ( \ + "mov r0, #255 << 4;" /* 256 entries/set */ \ + /* ((NSETS - 1) << (CIR[13-12] + 3)) */ \ + "2: " /* clean & invalidate D index */ \ + "mcr p15, 0, r0, c7, c14, 2;" \ + "subs r0, r0, #1 << 4;" \ + "bcs 2b;" /* entries 255 to 0 */ \ + "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \ + : \ + : \ : "r0" /* Clobber list */ \ ); \ CYG_MACRO_END #else # error "Don't know how to sync Dcache" diff -u -5 -p /dev/null packages/hal/arm/arm9/innovator/current/include/omap1510.h --- /dev/null 2002-08-30 19:31:37.000000000 -0400 +++ packages/hal/arm/arm9/innovator/current/include/omap1510.h 2003-03-31 15:19:51.000000000 -0500 @@ -0,0 +1,342 @@ +#ifndef CYGONCE_OMAP1510_H +#define CYGONCE_OMAP1510_H + +//============================================================================= +// +// omap1510.h +// +// Platform support (register layout, etc) specific to the OMAP1510 +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle +// Contributors: Patrick Doyle +// Date: 2003-02-18 +// Purpose: OMAP platform specific support definitions +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// This file does not belong in this directory, but it might as well stay +// here for now -- we can move it when we port eCos to the next OMAP +// based device. +//============================================================================= + +// Memory mapping +#define FLASH_CS0_BASE 0x00000000 +#define FLASH_CS1_BASE 0x04000000 +#define FLASH_CS2_BASE 0x08000000 +#define FLASH_CS3_BASE 0x0C000000 +#define SDRAM_BASE 0x10000000 +#define INTERNAL_SRAM_BASE 0x20000000 +#define MPUI_PORT_RAM 0xe0000000 + +// MPU Interface (i.e. to the DSP) +#define MPUI_BASE 0xFFFEC900 +#define _MPUI_CTRL_REG 0x00 +#define _MPUI_DEBUG_ADDR 0x04 +#define _MPUI_DEBUG_DATA 0x08 +#define _MPUI_DEBUG_FLAG 0x0C +#define _MPUI_STATUS_REG 0x10 +#define _MPUI_DSP_STATUS_REG 0x14 +#define _MPUI_DSP_BOOT_CONFIG 0x18 +#define _MPUI_DSP_API_CONFIG 0x1C + +#define MPUI_CTRL_REG (volatile long *)(MPUI_BASE + _MPUI_CTRL_REG) +#define MPUI_DEBUG_ADDR (volatile long *)(MPUI_BASE + _MPUI_DEBUG_ADDR) +#define MPUI_DEBUG_DATA (volatile long *)(MPUI_BASE + _MPUI_DEBUG_DATA) +#define MPUI_DEBUG_FLAG (volatile long *)(MPUI_BASE + _MPUI_DEBUG_FLAG) +#define MPUI_STATUS_REG (volatile long *)(MPUI_BASE + _MPUI_STATUS_REG) +#define MPUI_DSP_STATUS_REG (volatile long *)(MPUI_BASE + _MPUI_DSP_STATUS_REG) +#define MPUI_DSP_BOOT_CONFIG (volatile long *)(MPUI_BASE +_MPUI_DSP_BOOT_CONFIG) +#define MPUI_DSP_API_CONFIG (volatile long *)(MPUI_BASE + _MPUI_DSP_API_CONFIG) + +// CLKM Registers +#define CLKM_BASE 0xFFFECE00 +#define _CLKM_ARM_CKCTL 0x00 +#define _CLKM_ARM_IDLECT1 0x04 +#define _CLKM_ARM_IDLECT2 0x08 +#define _CLKM_ARM_EWUPCT 0x0C +#define _CLKM_ARM_RSTCT1 0x10 +#define _CLKM_ARM_RSTCT2 0x14 +#define _CLKM_ARM_SYSST 0x18 + +#define CLKM_ARM_CKCTL (volatile short *)(CLKM_BASE + _CLKM_ARM_CKCTL) +#define CLKM_ARM_IDLECT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT1) +#define CLKM_ARM_IDLECT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT2) +#define CLKM_ARM_EWUPCT (volatile short *)(CLKM_BASE + _CLKM_ARM_EWUPCT) +#define CLKM_ARM_RSTCT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT1) +#define CLKM_ARM_RSTCT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT2) +#define CLKM_ARM_SYSST (volatile short *)(CLKM_BASE + _CLKM_ARM_SYSST) + +// Watchdog Registers +#define WATCHDOG_BASE 0xFFFEC800 +#define _WD_CNTL_TIMER 0x00 +#define _WD_LOAD_TIM 0x04 +#define _WD_READ_TIM 0x04 +#define _WD_TIMER_MODE 0x08 + +#define WATCHDOG_CNTL_TIMER (volatile short *)(WATCHDOG_BASE + _WD_CNTL_TIMER) +#define WATCHDOG_LOAD_TIM (volatile short *)(WATCHDOG_BASE + _WD_LOAD_TIM) +#define WATCHDOG_READ_TIM (volatile short *)(WATCHDOG_BASE + _WD_READ_TIM) +#define WATCHDOG_TIMER_MODE (volatile short *)(WATCHDOG_BASE + _WD_TIMER_MODE) + +// Timer Registers +#define TIMER1_BASE 0xFFFEC500 +#define TIMER2_BASE 0xFFFEC600 +#define TIMER3_BASE 0xFFFEC700 +#define _TIM_CNTL_TIMER 0x00 +#define _TIM_LOAD_TIM 0x04 +#define _TIM_READ_TIM 0x08 + +#define TIMER1_CNTL_TIMER (volatile cyg_uint32 *)(TIMER1_BASE + _TIM_CNTL_TIMER) +#define TIMER1_LOAD_TIM (volatile cyg_uint32 *)(TIMER1_BASE + _TIM_LOAD_TIM) +#define TIMER1_READ_TIM (volatile cyg_uint32 *)(TIMER1_BASE + _TIM_READ_TIM) + +#define TIMER2_CNTL_TIMER (volatile cyg_uint32 *)(TIMER2_BASE + _TIM_CNTL_TIMER) +#define TIMER2_LOAD_TIM (volatile cyg_uint32 *)(TIMER2_BASE + _TIM_LOAD_TIM) +#define TIMER2_READ_TIM (volatile cyg_uint32 *)(TIMER2_BASE + _TIM_READ_TIM) + +#define TIMER3_CNTL_TIMER (volatile cyg_uint32 *)(TIMER3_BASE + _TIM_CNTL_TIMER) +#define TIMER3_LOAD_TIM (volatile cyg_uint32 *)(TIMER3_BASE + _TIM_LOAD_TIM) +#define TIMER3_READ_TIM (volatile cyg_uint32 *)(TIMER3_BASE + _TIM_READ_TIM) + +// Interrupt Handlers +#define IH1_BASE 0xFFFECB00 +#define IH2_BASE 0xFFFE0000 +#define _IH_ITR 0x00 +#define _IH_MIR 0x04 +#define _IH_SIR_IRQ_CODE 0x10 +#define _IH_SIR_FIQ_CODE 0x14 +#define _IH_CONTROL_REG 0x18 +#define _IH_ILR00 0x1C +#define _IH_ILR01 0x20 +#define _IH_ILR02 0x24 +#define _IH_ILR03 0x28 +#define _IH_ILR04 0x2C +#define _IH_ILR05 0x30 +#define _IH_ILR06 0x34 +#define _IH_ILR07 0x38 +#define _IH_ILR08 0x3C +#define _IH_ILR09 0x40 +#define _IH_ILR10 0x44 +#define _IH_ILR11 0x48 +#define _IH_ILR12 0x4C +#define _IH_ILR13 0x50 +#define _IH_ILR14 0x54 +#define _IH_ILR15 0x58 +#define _IH_ILR16 0x5C +#define _IH_ILR17 0x60 +#define _IH_ILR18 0x64 +#define _IH_ILR19 0x68 +#define _IH_ILR20 0x6C +#define _IH_ILR21 0x70 +#define _IH_ILR22 0x74 +#define _IH_ILR23 0x78 +#define _IH_ILR24 0x7C +#define _IH_ILR25 0x80 +#define _IH_ILR26 0x84 +#define _IH_ILR27 0x88 +#define _IH_ILR28 0x8C +#define _IH_ILR29 0x90 +#define _IH_ILR30 0x94 +#define _IH_ILR31 0x98 +#define _IH_ISR 0x9C + +#define IH1_ITR (volatile cyg_uint32 *)(IH1_BASE + _IH_ITR) +#define IH1_MIR (volatile cyg_uint32 *)(IH1_BASE + _IH_MIR) +#define IH1_SIR_IRQ_CODE (volatile cyg_uint32 *)(IH1_BASE + _IH_SIR_IRQ_CODE) +#define IH1_SIR_FIQ_CODE (volatile cyg_uint32 *)(IH1_BASE + _IH_SIR_FIQ_CODE) +#define IH1_CONTROL_REG (volatile cyg_uint32 *)(IH1_BASE + _IH_CONTROL_REG) +#define IH1_ILR00 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR00) +#define IH1_ILR01 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR01) +#define IH1_ILR02 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR02) +#define IH1_ILR03 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR03) +#define IH1_ILR04 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR04) +#define IH1_ILR05 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR05) +#define IH1_ILR06 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR06) +#define IH1_ILR07 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR07) +#define IH1_ILR08 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR08) +#define IH1_ILR09 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR09) +#define IH1_ILR10 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR10) +#define IH1_ILR11 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR11) +#define IH1_ILR12 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR12) +#define IH1_ILR13 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR13) +#define IH1_ILR14 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR14) +#define IH1_ILR15 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR15) +#define IH1_ILR16 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR16) +#define IH1_ILR17 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR17) +#define IH1_ILR18 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR18) +#define IH1_ILR19 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR19) +#define IH1_ILR20 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR20) +#define IH1_ILR21 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR21) +#define IH1_ILR22 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR22) +#define IH1_ILR23 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR23) +#define IH1_ILR24 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR24) +#define IH1_ILR25 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR25) +#define IH1_ILR26 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR26) +#define IH1_ILR27 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR27) +#define IH1_ILR28 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR28) +#define IH1_ILR29 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR29) +#define IH1_ILR30 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR30) +#define IH1_ILR31 (volatile cyg_uint32 *)(IH1_BASE + _IH_ILR31) +#define IH1_ISR (volatile cyg_uint32 *)(IH1_BASE + _IH_ISR) + +#define IH2_ITR (volatile cyg_uint32 *)(IH2_BASE + _IH_ITR) +#define IH2_MIR (volatile cyg_uint32 *)(IH2_BASE + _IH_MIR) +#define IH2_SIR_IRQ_CODE (volatile cyg_uint32 *)(IH2_BASE + _IH_SIR_IRQ_CODE) +#define IH2_SIR_FIQ_CODE (volatile cyg_uint32 *)(IH2_BASE + _IH_SIR_FIQ_CODE) +#define IH2_CONTROL_REG (volatile cyg_uint32 *)(IH2_BASE + _IH_CONTROL_REG) +#define IH2_ILR0 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR00) +#define IH2_ILR1 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR01) +#define IH2_ILR2 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR02) +#define IH2_ILR3 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR03) +#define IH2_ILR4 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR04) +#define IH2_ILR5 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR05) +#define IH2_ILR6 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR06) +#define IH2_ILR7 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR07) +#define IH2_ILR8 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR08) +#define IH2_ILR9 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR09) +#define IH2_ILR10 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR10) +#define IH2_ILR11 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR11) +#define IH2_ILR12 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR12) +#define IH2_ILR13 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR13) +#define IH2_ILR14 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR14) +#define IH2_ILR15 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR15) +#define IH2_ILR16 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR16) +#define IH2_ILR17 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR17) +#define IH2_ILR18 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR18) +#define IH2_ILR19 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR19) +#define IH2_ILR20 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR20) +#define IH2_ILR21 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR21) +#define IH2_ILR22 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR22) +#define IH2_ILR23 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR23) +#define IH2_ILR24 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR24) +#define IH2_ILR25 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR25) +#define IH2_ILR26 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR26) +#define IH2_ILR27 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR27) +#define IH2_ILR28 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR28) +#define IH2_ILR29 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR29) +#define IH2_ILR30 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR30) +#define IH2_ILR31 (volatile cyg_uint32 *)(IH2_BASE + _IH_ILR31) +#define IH2_ISR (volatile cyg_uint32 *)(IH2_BASE + _IH_ISR) + +#define IH_INT_PRIORITY_LVL_mask 0x0000007C + +/* Nothing below this line has been scrubbed yet */ + +/* Believe it or not, these actually make the code more readable in a few + * places. + */ +#ifndef BIT_00 +#define BIT_00 0x00000001 +#define BIT_01 0x00000002 +#define BIT_02 0x00000004 +#define BIT_03 0x00000008 +#define BIT_04 0x00000010 +#define BIT_05 0x00000020 +#define BIT_06 0x00000040 +#define BIT_07 0x00000080 +#define BIT_08 0x00000100 +#define BIT_09 0x00000200 +#define BIT_10 0x00000400 +#define BIT_11 0x00000800 +#define BIT_12 0x00001000 +#define BIT_13 0x00002000 +#define BIT_14 0x00004000 +#define BIT_15 0x00008000 +#define BIT_16 0x00010000 +#define BIT_17 0x00020000 +#define BIT_18 0x00040000 +#define BIT_19 0x00080000 +#define BIT_20 0x00100000 +#define BIT_21 0x00200000 +#define BIT_22 0x00400000 +#define BIT_23 0x00800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 +#endif + +#ifdef ARE_THESE_USED +/* DPLL Registers */ +#define DPLL1_BASE 0xFFFECF00 +#define DPLL2_BASE 0xFFFED000 +#define DPLL3_BASE 0xFFFED100 + +#define _DPLL_CTL_REG 0x00 + +#define DPLL1_CTL_REG (volatile short *)(DPLL1_BASE + _DPLL_CTL_REG) +#define DPLL2_CTL_REG (volatile short *)(DPLL2_BASE + _DPLL_CTL_REG) +#define DPLL3_CTL_REG (volatile short *)(DPLL3_BASE + _DPLL_CTL_REG) + +#define FPGA_BASE 0x08000000 /* CS2_BASE */ +#define CONFIG_BASE 0xFFFE1000 +#define TC_BASE 0xFFFECC00 + +/* FPGA Registers */ +#define FPGA_PWR_CTRL_REG (*(volatile char *)(FPGA_BASE + 0x05)) + +/* Configuration Registers */ +#define CONFIG_FUNC_MUX_CTRL_0 (*(volatile unsigned *)(CONFIG_BASE + 0x00)) +#define CONFIG_FUNC_MUX_CTRL_1 (*(volatile unsigned *)(CONFIG_BASE + 0x04)) +#define CONFIG_FUNC_MUX_CTRL_2 (*(volatile unsigned *)(CONFIG_BASE + 0x08)) + +/* Traffic Controller Registers */ +#define TC_IMIF_PRIO (*(volatile unsigned *)(TC_BASE + 0x00)) +#define TC_EMIFS_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x04)) +#define TC_EMIFF_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x08)) +#define TC_EMIFS_CONFIG_REG (*(volatile unsigned *)(TC_BASE + 0x0C)) +#define TC_EMIFS_CS0_CONFIG (*(volatile unsigned *)(TC_BASE + 0x10)) +#define TC_EMIFS_CS1_CONFIG (*(volatile unsigned *)(TC_BASE + 0x14)) +#define TC_EMIFS_CS2_CONFIG (*(volatile unsigned *)(TC_BASE + 0x18)) +#define TC_EMIFS_CS3_CONFIG (*(volatile unsigned *)(TC_BASE + 0x1C)) +#define TC_EMIFF_SDRAM_CONFIG (*(volatile unsigned *)(TC_BASE + 0x20)) +#define TC_EMIFF_MRS (*(volatile unsigned *)(TC_BASE + 0x24)) +#define TC_TIMEOUT1 (*(volatile unsigned *)(TC_BASE + 0x28)) +#define TC_TIMEOUT2 (*(volatile unsigned *)(TC_BASE + 0x2C)) +#define TC_TIMEOUT3 (*(volatile unsigned *)(TC_BASE + 0x30)) +#define TC_ENDIANISM (*(volatile unsigned *)(TC_BASE + 0x34)) + +#endif // ARE_THESE_USED +#endif // CYGONCE_OMAP_H +//-----------------------------------------------------------------------------