--- ecos-cvs/packages/hal/powerpc/ppc40x/current/src/hal_diag.c	2005-08-25 16:06:08.000000000 +0200
+++ ecos/packages/hal/powerpc/ppc40x/current/src/hal_diag.c	2005-09-06 08:47:44.000000000 +0200
@@ -75,13 +75,20 @@
 
 //-----------------------------------------------------------------------------
 // There are two serial ports.
-#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP)
-#define CYG_DEV_SERIAL_BASE_A    _PPC405GP_UART0
-#define CYG_DEV_SERIAL_BASE_B    _PPC405GP_UART1
-#endif
 #if defined(CYGHWR_HAL_POWERPC_PPC4XX_405EP)
 #define CYG_DEV_SERIAL_BASE_A    _PPC405EP_UART0
 #define CYG_DEV_SERIAL_BASE_B    _PPC405EP_UART1
+#define UCR0_MASK       0x0000007f
+#define UCR0_UDIV_POS   0
+#else /* defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP) */
+#define CYG_DEV_SERIAL_BASE_A    _PPC405GP_UART0
+#define CYG_DEV_SERIAL_BASE_B    _PPC405GP_UART1
 #endif
 //-----------------------------------------------------------------------------
 // Define the serial registers. The PPC405GP has 16552 UART(s) builtin.
@@ -164,12 +171,19 @@
 int
 cyg_var_baud_generator(int baud)
 {
-    int clock_rate, baud_clock, clock_divisor;
-    unsigned int cr0;
+    cyg_uint32 clock_rate, clock_divisor, cr0;
+    cyg_uint8 baud_clock;
 
     // Calculate baud rate clock divisor
+#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405EP)
+    /* CPC0_UCR_BASE 25:31 (7Bit) U0DIV 17:23 (7bit) U1DIV */
+    CYGARC_MFDCR(DCR_CPC0_UCR_BASE, cr0);
+    clock_divisor = (cr0 & UCR0_MASK) >> UCR0_UDIV_POS;
+#else
+    /* CPC0_CR0 26:30 (5Bit) generic UART divisor */
     CYGARC_MFDCR(DCR_CPC0_CR0, cr0);
     clock_divisor = ((cr0 & 0x3E) >> 1) + 1;
+#endif
     clock_rate = ((CYGHWR_HAL_POWERPC_CPU_SPEED*1000000)/clock_divisor);
     baud_clock = ((clock_rate)/16)/baud;
     return baud_clock;
@@ -182,34 +196,40 @@
 {
     cyg_uint8* base = __ch_data->base;
     cyg_uint8 lcr;
-    int baud_clock = cyg_var_baud_generator(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
+    cyg_uint8 baud_clock = cyg_var_baud_generator(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
 
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, 0);
 
-    // Disable and clear FIFOs (need to enable to clear).
+    /* Disable and clear FIFOs (need to enable to clear). */
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
                     (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0);
 
-    // 8-1-no parity.
+    /* 8-1-no parity. */
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
-    // Set speed to the default baud rate
+    /* Set DLAB Bit */
     HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
     lcr |= SIO_LCR_DLAB;
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
 
-    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, baud_clock & 0xFF);
-    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, (baud_clock >> 8) & 0xFF);
+    /* Set speed to the default baud rate */
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, baud_clock);
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, baud_clock >> 8);
+
+    /* Clear DLAB Bit */
     lcr &= ~SIO_LCR_DLAB;
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
 
-    // Enable FIFOs (and clear them).
+    /* Enable FIFOs (and clear them). */
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
                     (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
 
-    // Assert handshake signals
+    /* Assert handshake signals */
     HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR, (SIO_MCR_DTR|SIO_MCR_RTS));
+
+    /* Clear scratchpad */
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_SCR, 0);
 }
 
 static cyg_bool