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[PATCH] [AArch64] Optional trapping exceptions support
- From: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- To: libc-alpha at sourceware dot org
- Cc: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Thu, 6 Mar 2014 13:19:48 +0000
- Subject: [PATCH] [AArch64] Optional trapping exceptions support
- Authentication-results: sourceware.org; auth=none
Hi,
Trapping exceptions in AArch64 are optional. The relevant exception
control bits in FPCR are are defined as RES0 hence the absence of
support can be detected by reading back the FPCR and comparing with
the desired value.
Tested aarch64-none-linux-gnu, no regressions.
I'll leave this on the list for 24h before committing.
Cheers
/Marcus
---
ChangeLog | 6 ++++++
sysdeps/aarch64/fpu/feenablxcpt.c | 13 +++++++++++++
sysdeps/aarch64/fpu/fesetenv.c | 10 ++++++++++
3 files changed, 29 insertions(+)
diff --git a/ChangeLog b/ChangeLog
index b595d64..7901d89 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2014-03-06 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): Detect and
+ error absence of trapping exception support.
+ * sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Likewise.
+
2014-03-05 Joseph Myers <joseph@codesourcery.com>
* math/libm-test.inc (max_valid_error): New variable.
diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index d976999..07a4bbb 100644
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -35,5 +35,18 @@ feenableexcept (int excepts)
_FPU_SETCW (fpcr);
+ /* Trapping exceptions are optional in AArch64 the relevant enable
+ bits in FPCR are RES0 hence the absence of support can be
+ detected by reading back the FPCR and comparing with the required
+ value. */
+ if (excepts)
+ {
+ fpu_control_t updated_fpcr;
+
+ _FPU_GETCW (updated_fpcr);
+ if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+ return -1;
+ }
+
return original_excepts;
}
diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c
index 443c705..a2434e3 100644
--- a/sysdeps/aarch64/fpu/fesetenv.c
+++ b/sysdeps/aarch64/fpu/fesetenv.c
@@ -24,6 +24,7 @@ fesetenv (const fenv_t *envp)
{
fpu_control_t fpcr;
fpu_fpsr_t fpsr;
+ fpu_control_t updated_fpcr;
_FPU_GETCW (fpcr);
_FPU_GETFPSR (fpsr);
@@ -51,6 +52,15 @@ fesetenv (const fenv_t *envp)
_FPU_SETCW (fpcr);
+ /* Trapping exceptions are optional in AArch64 the relevant enable
+ bits in FPCR are RES0 hence the absence of support can be
+ detected by reading back the FPCR and comparing with the required
+ value. */
+
+ _FPU_GETCW (updated_fpcr);
+ if ((updated_fpcr & fpcr) != fpcr)
+ return 1;
+
return 0;
}
--
1.7.9.5