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[PATCH] Support non-inclusive caches on Intel processors
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: GNU C Library <libc-alpha at sourceware dot org>
- Date: Wed, 11 May 2016 13:00:08 -0700
- Subject: [PATCH] Support non-inclusive caches on Intel processors
- Authentication-results: sourceware.org; auth=none
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Tested on Intel processors with inclusive cache and non-inclusive cache.
OK for master?
H.J.
--
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
non-inclusive caches on Intel processors.
---
sysdeps/x86/cacheinfo.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 143b333..8408624 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -492,6 +492,9 @@ init_cacheinfo (void)
{
data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
+ long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ bool inclusive_cache = true;
+
/* Try L3 first. */
level = 3;
shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
@@ -500,7 +503,7 @@ init_cacheinfo (void)
{
/* Try L2 otherwise. */
level = 2;
- shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ shared = core;
}
/* Figure out the number of logical threads that share the
@@ -526,6 +529,9 @@ init_cacheinfo (void)
}
while (((eax >> 5) & 0x7) != level);
+ /* Check if cache is inclusive of lower cache levels. */
+ inclusive_cache = (edx & 0x2) != 0;
+
threads = (eax >> 14) & 0x3ff;
/* If max_cpuid >= 11, THREADS is the maximum number of
@@ -592,6 +598,10 @@ init_cacheinfo (void)
threads. */
if (shared > 0 && threads > 0)
shared /= threads;
+
+ /* Account for non-inclusive L2 and L3 caches. */
+ if (level == 3 && !inclusive_cache)
+ shared += core;
}
/* This spells out "AuthenticAMD". */
else if (is_amd)
--
2.5.5