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Re: riscv: fmax/fmin sNaN fix
- From: DJ Delorie <dj at redhat dot com>
- To: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- Cc: libc-alpha at sourceware dot org, nd at arm dot com
- Date: Tue, 20 Feb 2018 12:12:30 -0500
- Subject: Re: riscv: fmax/fmin sNaN fix
- Authentication-results: sourceware.org; auth=none
Szabolcs Nagy <szabolcs.nagy@arm.com> writes:
> On 20/02/18 02:57, DJ Delorie wrote:
>>
>> RISC-V's FPU follows the IEEE spec, not the POSIX spec. This patch
> ^^^^^^^^^
> which one?
> (the next ieee revision will have different min/max operations)
The one that doesn't match POSIX :-)
The RISC-V fpu does this:
fmax (sNAN,4) -> 4
GLIBC expects this:
fmax (sNAN,4) -> qNAN
(hmm... maybe it follows posix, not ieee... whatever, it doesn't do what
glibc expects)
Note that the RISC-V ISA spec 2.2 documents the sNAN->qNAN behavior,
there's a patch for 2.3 that corrects it to match actual hardware.