This is the mail archive of the
libc-alpha@sourceware.org
mailing list for the glibc project.
Re: [PATCH] mips: Do not include hi and lo in __SYSCALL_CLOBBERS for R6
- From: Joseph Myers <joseph at codesourcery dot com>
- To: Dragan Mladjenovic <dmladjenovic at wavecomp dot com>
- Cc: "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>
- Date: Tue, 19 Nov 2019 16:57:03 +0000
- Subject: Re: [PATCH] mips: Do not include hi and lo in __SYSCALL_CLOBBERS for R6
- Ironport-sdr: v0HjFk2pEQ3jbOhRuOfOrNMZkboxMUDl7j1vLpgXAuRoYErnf5wL1pdO7+454w7bMKvDGbtAlp K8g0gVTZDgEYEN8TMxz9nUvHS6KogRTrYm46sgG1GP1Ze45VKODWjN6Qepx/b6gwKbNHdRKTLW wWHlHpCJ7GQqe4OoivJ8W9XLFK5PR99KtxGfAgsg0g7nZlL0OFOf9bme+U+rXGWuY356j5wb2/ yiFkmaRs0q0KhPaxSkl01hwmmC0uYQdCdLXgUt5ekY9jo1aXnKVpkJ60+qBwsGSR4MRn40v8Fp RH4=
- Ironport-sdr: 20yofhkZPcumoNUcG7ujm/UEKGZ2mhVzTTXKOh/RqvoXsHWnmqlQNMXuce69A8WGb5lgtSgQHd ji3KbtnMz57J4h9Gc8uI+9tn79JJ2qxFC0BWA+ooBdFtWyE90TZ/LGVvym81o44MWvFIPL5YMs Ioj8kR056soKpAFeWNRZOdcuROCUR6zpK2HG7NxdAzVEEAjl6zRvK9bfMgUyGluA7WGwm6MZZz w92VVb/a3ah7L6js32q1WFnSjJ9sxrCdkRs+IryYFAFmmoC8Vzc6uPSn5+eXDf3nh3T4OstM7Y kuc=
- References: <1574175364-5601-1-git-send-email-dmladjenovic@wavecomp.com>
On Tue, 19 Nov 2019, Dragan Mladjenovic wrote:
> From: "Dragan Mladjenovic" <dmladjenovic@wavecomp.com>
>
> GCC 10 (PR 91233) won't silently allow registers that are not architecturally
> available to be present in the clobber list anymore, resulting in build failure
> for mips*r6 targets in form of:
> ...
> .../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target
> 146 | __asm__ volatile ( \
> | ^~~~~~~
>
> This is because base R6 ISA doesn't define hi and lo registers w/o DSP
> extension. This patch provides the alternative definitions of
> __SYSCALL_CLOBBERS for r6 targets that won't include those registers.
What is the kernel ABI on r6 systems with the DSP extension - does the
kernel ABI permit the kernel to clobber those registers on syscall return
or not? This patch looks like it's only safe if the kernel guarantees it
will never clobber those registers on r6 (or later), regardless of
instruction set extensions present.
Also, this issue suggests that build-many-glibcs.py ought to include MIPS
r6 configurations to detect such build issues. It might not be a good
idea to duplicate all 24 ABIs for r6 (I don't know how many of them make
sense for r6 anyway), but at least one each of o32, n32 and n64 for r6 (if
all those make sense for r6) would be a good idea. (build-many-glibcs.py
additions should be a separate patch.)
--
Joseph S. Myers
joseph@codesourcery.com