Re: [PATCH 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors

["May Shao(BJ-RD)" <MayShao at zhaoxin dot com>]

On 09/12/2019 4:34 pm, Florian Weimer wrote:
> * MayShao:
>
>> +                 cpu_features->feature[index_arch_Slow_SSE4_2]
>> +                   |= (bit_arch_Slow_SSE4_2
>> +                   | bit_arch_Prefer_MAP_32BIT_EXEC);
>
> Is the Prefer_MAP_32BIT_EXEC part really correct?

As glibc comments for this macro below:

"For 64-bit applications, branch prediction performance may be
negatively impacted when the target of a branch is more than
4GB away from the branch"

We have analyzed this generation of processors and found it have
this issue in theory, so we add this flag for it.

> As discussed recently, it does not have an effect with programs linked
> with -z separate-code (the default these days, I think) and PIE.

Do you mean the above macro will be ignored if program linked
with -z separate-code and PIE?

If it does, is there any harms if keep this macro? thanks a lot!

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>
> Would you please clarify if this is intended as a patch submission?

Sorry for any inconvenience, it's appended by mail sever automatically,
please ignore it.

Thanks for the review.


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