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Re: [PATCH] powerpc: Move cache line size to rtld_global_ro
- From: Shawn Landden <shawn at git dot icu>
- To: Florian Weimer <fweimer at redhat dot com>, Tulio Magno Quites Machado Filho <tuliom at ascii dot art dot br>
- Cc: "law at redhat dot com" <law at redhat dot com>, Adhemerval Zanella <adhemerval dot zanella at linaro dot org>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>
- Date: Fri, 10 Jan 2020 11:09:42 -0500
- Subject: Re: [PATCH] powerpc: Move cache line size to rtld_global_ro
- References: <mvmh82xeg6n.fsf@suse.de> <20191223184523.70113-1-tuliom@linux.ibm.com> <b719ad08-c818-7963-1b10-341f04af7c5e@linaro.org> <875zi16ai8.fsf@linux.ibm.com> <2fb22e3b-cc59-24e8-661b-6da39371bb84@linaro.org> <87zhew9b32.fsf@oldenburg2.str.redhat.com> <b8ad6fed0495158c4ea4e9ded99986cf688d9944.camel@redhat.com> <87pnfso8bi.fsf@linux.ibm.com> <87lfqf3b2l.fsf@oldenburg2.str.redhat.com>
Not trying to say anything stupid, but why can't we just detect the cache line size using the "dcbz" instruction, as documented in the PowerISA document? It is because the ancient G5 also has a "dcbzl" instruction that clears a wider size (the actually cache line size)?
--
Shawn Landden