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[RFC 05/13] mips: Special get_cycles for cavium octeon
- From: Crestez Dan Leonard <cdleonard at gmail dot com>
- To: systemtap at sourceware dot org
- Date: Thu, 31 Jul 2014 23:21:10 +0300
- Subject: [RFC 05/13] mips: Special get_cycles for cavium octeon
- Authentication-results: sourceware.org; auth=none
- References: <cover dot 1406837921 dot git dot cdleonard at gmail dot com>
- References: <cover dot 1406837921 dot git dot cdleonard at gmail dot com>
Originally part of a bigger patch by Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Crestez Dan Leonard <cdleonard@gmail.com>
---
runtime/time.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/runtime/time.c b/runtime/time.c
index b4c2012..284f542 100644
--- a/runtime/time.c
+++ b/runtime/time.c
@@ -40,6 +40,22 @@ static int __stp_cpufreq_notifier_registered = 0;
STP_TIME_SYNC_INTERVAL_NOCPUFREQ)
#endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+/* Octeon supports a 64 bit cycle counter we might as well use it */
+static inline cycles_t octeon_get_cycles(void)
+{
+ cycles_t result;
+ asm volatile ("rdhwr %0,$31\n"
+#ifndef CONFIG_64BIT
+ "sll %0,0\n"
+#endif
+ : "=r" (result));
+ return result;
+}
+#define get_cycles octeon_get_cycles
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
+
+
#ifndef NSEC_PER_MSEC
#define NSEC_PER_MSEC 1000000L
#endif