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Re: [PATCH 1/3] Update s_sincosf.c and x86-64 s_sincosf-fma.c
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- Cc: Adhemerval Zanella <adhemerval dot zanella at linaro dot org>, "szabolcs.nagy" <Szabolcs dot Nagy at arm dot com>, GNU C Library <libc-alpha at sourceware dot org>, nd <nd at arm dot com>
- Date: Mon, 3 Dec 2018 06:32:50 -0800
- Subject: Re: [PATCH 1/3] Update s_sincosf.c and x86-64 s_sincosf-fma.c
- References: <DB5PR08MB103013E47FB0CAF1DA7FE8B883AE0@DB5PR08MB1030.eurprd08.prod.outlook.com>
On Mon, Dec 3, 2018 at 4:13 AM Wilco Dijkstra <Wilco.Dijkstra@arm.com> wrote:
>
> Hi Adhemerval,
>
> > I did check on a A53 I saw no regressions with benchtests. Do you see any
> > regressions on other chips or systems?
>
> Cortex-A53 doesn't support 128-bit loads, however most other AArch64 cores do.
>
> > If it is the case one option could be use my suggestion to move s_sincosf_t
> > to its own header.
>
> Well there is no need to change the existing structure, it's small so the vector
> version could just add a new structure. In fact I can't see why any of this should
Only sincosf_poly is vectorized. Without changing the existing
structure, I need
to duplicate everything in sysdeps/ieee754/flt-32/s_sincosf.h.
> be target specific. GCC supports generic vector notation, so that should be the
> obvious approach for this optimization.
>
My x86-64 vector version has x86-64 specific intrinsics:
__v2df vps1c2 = (__v2df) _mm_loadu_pd (&p->s1c2.s1);
__v2df vps2c3 = (__v2df) _mm_loadu_pd (&p->s2c3.s2);
__v2df vps3c4 = (__v2df) _mm_loadu_pd (&p->s3c4.s3);
__v4sf v4sf = _mm_cvtpd_ps (vsincos);
--
H.J.